SN54/74LS569A
FOUR-BIT UP/DOWN COUNTER
WITH THREE-STATE OUTPUTS
The SN54 / 74LS569A is designed as programmable up/down BCD and
Binary counters respectively. These devices have 3-state outputs for use in
bus organized systems. With the exception of output enable (OE) and
asynchronous clear (ACLR), all functions occur on the positive edge of the
clock pulse (CP).
When the LOAD input is LOW, the outputs will be programmed by the
parallel data inputs (A, B, C, D) on the next clock edge. Enabling of the
counters occurs only when CEP and CET are LOW and LOAD is HIGH.
Direction of the count is controlled by the up-down input (U/D), HIGH counts
up and LOW counts down. High-speed counting and cascading is implement-
ed by internal look-ahead carry logic and an active LOW ripple carry output
(RCO). On the LS569A, the RCO is LOW at binary 15 during up-count and
during down-count it is also LOW at binary 0. During normal cascading
operation RCO connected to the succeeding block at CET is the only
requisite. When counting and when RCO is LOW, the clocked carry output
(CCO) provides a HIGH-LOW-HIGH pulse for a duration equal to the LOW
time of the clock pulse. Two active LOW reset lines are provided, a master
reset asynchronous clear (ACLR) and a synchronous clear (SCLR). When in
a HIGH state, the output control (OE) input forces the counter output into a
HIGH impedance state and when LOW, the counter outputs are enabled.
FOUR-BIT UP/ DOWN COUNTER
WITH THREE-STATE OUTPUTS
LOW POWER SCHOTTKY
20
1
J SUFFIX
CERAMIC
CASE 732-03
20
1
N SUFFIX
PLASTIC
CASE 738-03
•
ESD > 3500 Volts
CONNECTION DIAGRAM
(TOP VIEW)
20
V
CC
20
RCO
19
CCO
18
OE
17
Y
A
16
Y
B
15
Y
C
14
Y
D
13
CET
12
LOAD
11
V
= PIN 20
CC
GND = PIN 10
DW SUFFIX
SOIC
CASE 751D-03
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
Note: Pin 1 is marked
for orientation.
1
U/D
2
CP
3
A
4
B
5
C
6
D
7
8
9
10
GND
CEP ACLR SCLR
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOH
IOL
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High Except RCO, CCO
Output Current — High RCO, CCO
Output Current — Low Except RCO, CCO
Output Current — Low, RCO, CCO
Parameter
54
74
54
74
54
74
54, 74
54
74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 1.0
– 2.6
– 0.44
12
24
4.0
8.0
Unit
V
°C
mA
mA
mA
mA
FAST AND LS TTL DATA
5-573
SN54/74LS569A
FUNCTION TABLE
INPUTS
CP
↑
↑
↑
↑
Ω
↑
↑
↑
↑
↑
↑
↑
↑
X
X
X
X
D C B A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
LOAD
H
H
H
H
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
CET
L
L
H
L
L
L
H
L
L
H
X
H
L
L
H
X
L
L
H
X
CEP
L
L
X
H
L
H
X
L
H
X
X
X
L
H
X
X
L
H
X
X
U/D
H
L
X
X
H
H
H
L
L
L
X
H
L
L
L
H
L
L
L
X
ACLR
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
X
SCLR
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
X
X
X
X
X
OE
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
RCO
A/R
A/R
H
A/R
L
L
H
L
L
H
H
H
L
L
H
H
L
L
H
X
CCO
A/R
A/R
H
H
H
H
H
H
H
H
H
H
H
H
H
X
OUTPUTS
YD
YC
YB
YA
Count Up
Count Down
Count Inhibit
Count Inhibit
Overflow
Overflow
Overflow Inhibit
Underflow
Underflow
Underflow Inhibit
Load Example
Clear (Synchronous)
Clear (Synchronous)
Clear (Synchronous)
Clear (Synchronous)
Asynchronous Clear
Asynchronous Clear
Asynchronous Clear
Asynchronous Clear
Output Disabled
(QT – CP) + 1
(QT – CP) – 1
NC NC NC NC
NC NC NC NC
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
H
L
L
L
L
L
L
L
L
Hi-Z
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
H
L
L
L
L
L
L
L
L
L H L H
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
(QT — CP) = Output state prior to clock edge
NC = No change
A/R = Assumes required output state;
High except during Overflow and Underflow
X = Don’t care
LOGIC DIAGRAM
OE
*
D
Q
ACLR
R
CP
Q
A
*
Y
A
B
*
Y
B
C
*
Y
C
D
SCLR
LOAD
*
Y
D
CEP
CET
CP
U/D
RCO
CCO
FAST AND LS TTL DATA
5-574
SN54/74LS569A
DEFINITION OF FUNCTIONAL TERMS
A, B, C, D
CEP
The four programmable data inputs.
Count Enable Parallel. Can be used to
enable and inhibit counting in high speed
cascaded operation. CEP must be LOW to
count.
Count Enable Trickle. Enables the ripple
carry output for cascaded operation. Must
be LOW to count.
Clock Pulse. All synchronous functions
occur on the LOW-to-HIGH transition of the
clock.
Enables parallel load of counter outputs
from data inputs on the next clock edge.
Must be HIGH to count.
Up/Down Count Control. HIGH counts up
and LOW counts down.
ACLR
Asynchronous Clear. Master reset of
counters to zero when ACLR is LOW,
independent of the clock.
Synchronous clear of counters to zero on
the next clock edge when SCLR is LOW.
A HIGH on the output control sets the four
counter outputs in the high impedance, and
a LOW, enables the output.
SCLR
OE
CET
CP
YA, YB, YC, YD The four counter outputs.
RCO
Ripple Carry Output. Output will be LOW on
the maximum count on up-count. Upon
down-count, RCO is LOW at 0000.
Clock Carry Output. While counting and
RCO is LOW, CCO will follow the clock
HIGH-LOW-HIGH transition.
LOAD
CCO
U/D
LOW-POWER SCHOTTKY INPUT/OUTPUT
CURRENT INTERFACE CONDITIONS
VCC
DRIVING OUTPUT
IOH
DRIVING OUTPUT
IOH IIL
DRIVEN INPUT
IOL
IOL IIH
Note: Actual current flow direction shown
FAST AND LS TTL DATA
5-575
SN54/74LS569A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
Parameter
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
Output HIGH Voltage
VOH
RCO,
CCO
YA–
YD
54
74
54
74
54, 74
VOL
IOZH
IOZL
IIH
Output LOW Voltage
74
Output Off Current HIGH
Output Off Current LOW
Input HIGH Current
0.1
Others
IIL
Input LOW Current
CET
Short Circuit Current
(Note 1)
RCO, CCO
Others
– 20
– 30
– 0.8
–100
– 130
43
mA
mA
mA
mA
VCC = MAX
VCC = MAX
– 0.4
0.35
0.5
20
– 20
20
V
µA
µA
µA
mA
mA
VCC = MAX, VIN = 0.4 V
2.4
2.4
2.5
2.7
– 0.65
3.4
3.1
3.5
3.5
0.25
0.4
0.8
– 1.5
V
V
V
V
V
V
IOL = IOL MAX
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
Min
2.0
0.7
V
Typ
Max
Unit
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MAX, VO = 2.7 V
VCC = MAX, VO = 0.4 V
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
IOS
ICC
Power Supply Current, 3-State
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
FAST AND LS TTL DATA
5-576
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Maximum Toggle Frequency
Propagation Delay
Clock to Q
Propagation Delay
CET to RCO
Propagation Delay
U/D to RCO
Propagation Delay
Clock to RCO
Propagation Delay
CET to CCO
Propagation Delay
CEP to CCO
Propagation Delay
Clock to CCO
Propagation Delay
ACLR to Q
Output Enable Time
Output Disable Time
35
15
20
14
15
20
24
20
25
16
28
16
26
15
17
22
32
15
20
20
27
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL = 5.0 pF
VCC = 5.0 V
CL = 45 pF
RL = 667
Ω
FAST AND LS TTL DATA
5-577
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