family. Designed to fit in a small 6-pin DFN, or 6-pin
SOT package for high performance applications, t he
PL611s-27 offers very low phase noise, jitter, and
power consumption, while offering 2 clock outputs.
The Frequency Switching (FSEL) capability of
PL611s-27 allows for programming two sets of
frequencies, while the power down feature of
PL611s-27, when activated, allows the IC to
consume less than 10µA of power. PL611s-27’s
programming flexibility allows generating any output
using a reference input signal.
PACKAGE PIN CONFIGURATION
CLK1
FIN
CLK1
GND
1
2
3
6
5
4
OE, PDB, FSEL
VDD
CLK0
PL611s-27
1
2
3
6
5
4
CLK0
VDD
OE, PDB, FSEL
PL611s-27
GND
FIN
DFN-6L
(2.0 x 1.3 x 0.6mm)
SOT23-6L
(3.0 x 3.0 x 1.35mm)
BLOCK DIAGRAM
FIN
F
REF
R-Counter
(8-bit)
M-Counter
(11-bit)
Phase
Detector
Charge
Pump
Loop
Filter
F
VCO
= F
REF
* (2 * M/R)
VCO
/2
P-Counter
(5-bit)
CLK0
F
OUT
= F
VCO
/ (2 * P)
CLK1
Programmable Function
Programming
Logic
OE, PDB,
FSEL
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1( 408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 7/7/08 Page 1
PL611s-27
1.8V to 3.3V PicoPLL
TM
Programmable Clock
KEY PROGRAMMING PARAM ETERS
CLK[0:1]
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
or CLK0
Output Drive Strength
Three optional drive strengths to
choose from:
Low: 4mA
Std: 8mA (default)
High: 16mA
Programmable
Input/Output
One pin can be configured as:
OE - input
PDB - input
FSEL – input
PACKAGE PIN ASSIGNMENT
Pin Assignment
Name
CLK1
GND
FIN
DFN
Pin#
2
3
1
SOT
Pin #
1
2
3
Type
O
P
I
Description
Programmable Clock Output. CLK1 = CLK0 or CLK1=F
REF
GND connection
Reference input pin
This programmable I/O pin can be configured as an Output Enable
(OE) input, Power Down (PDB) input or Frequency Switching (FSEL)
input.
6
4
I
State
0
1 (default)
VDD
CLK0
5
4
5
6
P
O
VDD connection
Programmable Clock Output
OE
Disable CLK
Normal mode
PDB
Power Down Mode
Normal mode
FSEL
Bank ‘0’
Bank ‘1’
OE,
PDB,
FSEL
OE AND PDB FUNCTION DESCRIPTION
CLK1
OE
1(Default)
0
N/A
N/A
PDB
N/A
N/A
1(Default)
0
Osc.
On
On
On
Off
PLL
On
Off
On
Off
CLK0
On
Active Low
On
Active Low
When
CLK1=F
REF
On
On
On
Active Low
When
CLK1=CLK0
On
Active Low
On
Active Low
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1( 408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 7/7/08 Page 2
PL611s-27
1.8V to 3.3V PicoPLL
TM
Programmable Clock
FUNCTIONAL DESCRIPTION
PL611s-27 is a highly featured, very flexible, advanced programmable PLL design for high performance, low -
power, small form-factor applications. The PL611s -27 accepts a reference clock input of 1MHz to 200MHz and is
capable of producing two outputs up to 125MHz. This flexible design allows the PL611s -27 to deliver any PLL
generated frequency, F
REF
(Ref Clk) frequency or F
REF
/(2*P) to CLK0 and/or CLK1. Some of the design features
of the PL611s-27 are mentioned below:
PLL Programming
The PLL in the PL611s -27 is fully programmable.
The PLL is equipped with an 8-bit input frequency
divider (R-Counter), and an 11-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 5-bit post VCO divider (P-
Counter). The output frequency is determined by
the following formula [F
OUT
= F
REF
* M / (R * P)].
Clock Output (CLK0)
CLK0 is the main clock output. The output of CLK0
can be configured as the PLL output (F
V CO
/(2*P)),
F
REF
(Ref Clk Frequency) output, or F
REF
/(2*P)
output. The output drive level can be programmed to
Low Drive (4mA), Standard Drive (8mA) or High Drive
(16mA). The maximum output frequency is 125MHz
(3.3V).
Clock Output (CLK1)
The CLK1 feature allows the PL611s -27 to have an
additional clock output. This output can be
programmed to one of the following:
F
REF
- Reference (Ref Clk) Frequency
CLK0
When using the OE function CLK1 will remain
“Always On” if programmed as F
REF
output and
will
not
be disabled when OE is pulled low. If CLK1 is
programmed to equal CLK0 then the output
will
disable when OE is pulled low. When using the PDB
function CLK1 will always be disabled along with
CLK0. The output drive level can be programmed to
Low Drive (4mA), Standard Drive (8mA) or High Drive
(16mA). The maximum output frequency is 125MHz
(3.3V).
Output Enable (OE)
The Output Enable feature allows the user to enabl e
and disable the CLK0 and/or CLK1 outputs by
toggling the OE pin.
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to
put the PL611s-27 into “Sleep Mode”. When
activated (logic ‘0’), PDB ‘Disables the PLL, the
oscillator circuitry, counters, and all other active
circuitry. In Power Down mode the IC consumes
<10µA of power.
Frequency Select (FSEL)
The Frequency Select (FSEL) feature allows th e
PL611s-27 to switch between two pre-programmed
banks allowing the device “On the Fly” frequency
switching.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1( 408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 7/7/08 Page 3
PL611s-27
1.8V to 3.3V PicoPLL
TM
Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature (Green package)
Data Retention @ 85C
Storage Temperature
Ambient Operating Temperature*
T
S
10
-65
-40
150
85
SYMBOL
V
DD
V
I
V
O
MIN.
-0.5
-0.5
-0.5
MAX.
7
V
DD
+0.5
V
DD
+0.5
260
UNITS
V
V
V
C
Year
C
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Input (FIN) Frequency
Input (FIN) Signal Amplitude
CONDITIONS
All operating voltages (see Input Signal
Amplitude restrictions below)
DC Coupled, LVCMOS input, High
DC Coupled, LVCMOS input, Low
0.9
0.1
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ V
DD
=3.3V
Output Frequency
Settling Time
Output Enable Time
Output Rise Time
Output Fall Time
Duty Cycle
@ V
DD
=2.5V
@ V
DD
=1.8V
At power-up (after V
DD
increases over 1.62V)
OE Function; Ta=25º C, 15pF Load. Add
one clock period to this measurement for a
usable clock output.
PDB Function; Ta=25º C, 15pF Load
15pF Load, 10/90% V
DD
, High Drive, 3.3V
15pF Load, 90/10% V
DD
, High Drive, 3.3V
V
DD
/ 2
45
1.2
1.2
50
70
MIN.
1
0.7*V
DD
0.3*V
DD
V
DD
V
DD
125
90
65
2
10
2
1.7
1.7
55
TYP.
MAX.
200
UNITS
MHz
Vpp
Vpp
Vpp
MHz
MHz
MHz
ms
ns
ms
ns
ns
%
ps
Input (FIN) Signal Amplitude Internally AC coupled (High Frequency)
Input (FIN) Signal Amplitude
Period Jitter,Pk-to-Pk*
Capacitive decoupling between V
DD
and
(10,000 samples measured) GND.
* Note: Jitter perform ance depends on the programming parameters.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1( 408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 7/7/08 Page 4
PL611s-27
1.8V to 3.3V PicoPLL
TM
Programmable Clock
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with
Loaded LVCMOS Outputs
Supply Current, Dynamic, with
Loaded LVCMOS Outputs
Supply Current, Dynamic with
Loaded LVCMOS Outputs
Stand By Current, with Loaded
Outputs
Operating Voltage
Power Supply Ramp
Output Low Voltage
Output High Voltage
Output Current, Low Drive
Output Current, Standard Drive
Output Current, High Drive
SYMBOL
I
DD
I
DD
I
DD
I
DD
V
DD
t
PU
V
OL
V
OH
I
OSD
I
OSD
I
OHD
Time for V
DD
to reach
90% V
DD
. Power ramp
must be monotonic.
I
OL
= +4mA Std Drive
I
OH
= -4mA Std Drive
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
DD
– 0.4
4
8
16
CONDITIONS
@ V
DD
=3.3V, 27MHz,
load=15pF
@ V
DD
=2.5V, 27MHz,
load=15pF
@ V
DD
=1.8V, 27MHz,
load=15pF
When PDB=0
1.62
MIN.
TYP.
5.5
3.8
1.8
<10
3.63
100
0.4
MAX.
UNITS
mA
mA
mA
µA
V
ms
V
V
mA
mA
mA
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1( 408) 944-0800 • fax +1(408) 474-1000 •
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