Low Phase Noise VCXO (17MHz to 36MHz)
FEATURES
VCXO output for the 17MHz to 36MHz range
Low phase noise (-130dBc @ 10kHz offset at
35.328MHz)
LVCMOS output with OE tri-state control
17 to 36MHz fundamental crystal input
Integrated high linearity variable capacitors
8mA drive capability at TTL output
±150 ppm pull range, max 5% (typ.) linearity
Low jitter (RMS): 2.5ps period jitter
2.5 to 3.3V operation
Available in 8-Pin SOP, 6-pin SOT23 GREEN/
RoHS compliant packages, or Die
PIN CONFIGURATION
XIN
VDD*
VCON
GND
1
2
3
4
8
7
6
5
XOUT
OE^
VDD*
CLK
SOP-8L
P500-17
SC
LLLLL
1
2
3
6
5
4
XOUT
XIN
VDD
VCON
B17
LLL
DESCRIPTION
The PLL500-17 is a low cost, high performance and
low phase noise VCXO for the 17 to 36MHz range,
providing less than -130dBc at 10kHz offset at
35.328MHz. The very low jitter (2.5 ps RMS period
jitter) makes this chip ideal for applications requiring
voltage controlled frequency sources. Input crystal
can range from 17 to 36MHz (fundamental resonant
mode).
GND
CLK
SOT23-6L
^: Denotes internal Pull-up
*: Only one VDD pin needs to be connected
BLOCK DIAGRAM
XIN
XOUT
VCON
OE
Xtal
Osc
CLK
Varicap
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/11/09 Page 1
Low Phase Noise VCXO (17MHz to 36MHz)
DIE PAD LAYOUT
32 mil
(812,986)
DIE SPECIFICATIONS
8
1
XIN
XOUT
OE^ 7
39 mil
Name
Size
Reverse side
Pad dimensions
Thickness
Value
39 x 32 mil
GND
80 micron x 80 micron
10 mil
2
VDD
VDD 6
3 VCON
CLK 5
4 GND
DIE ID:
C500xxxxxx
Y
X
(0,0)
Note: ^ denotes internal pull up
PACKAGE PIN AND DIE PAD ASSIGNMENT
Pin#
Name
XIN
VDD
VCON
GND
CLK
VDD
OE*
XOUT
SOP-8
1
2
3
4
5
6
7
8
SOT23-6
6
5
4
2
3
-
-
1
Die Pad Position
X (m)
94.183
94.157
94.183
94.193
715.472
715.307
715.472
476.906
Y (m)
768.599
605.029
331.756
140.379
203.866
455.726
626.716
888.881
Type
I
P
I
P
O
P
I
I
Description
Crystal input pin.
VDD power supply pin. Only one VDD pin is
necessary.
Frequency control voltage input pin.
Ground pin.
Output clock pin.
VDD power supply pin. Only one VDD pin is
necessary.
Output Enable input pin. Disables the output
when low. Internal pull-up enables output by
default if pin is not connected to low.
Crystal output pin. Ref Clock input.
* OE (Output Enable) pin is not available in SOT23-6L package, the output will always be enabled by the build in pull-up resister.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/11/09 Page 2
Low Phase Noise VCXO (17MHz to 36MHz)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Machine Model
ESD Protection, Human Body Model
200
2
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
-0.5
-0.5
-65
-40
MIN.
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
UNITS
V
V
V
C
C
C
C
V
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.*
Note:
Operating Temperature is guaranteed by design for all parts
(COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK Output Pullability
VCXO Tuning Characteristic
Pull Range Linearity
Power Supply Rejection
VCON Pin Input Impedance
VCON Modulation BW
0V
VCON
3.3V, -3dB
PWSRR
Frequency change, V
DD
±10%
-1
2000
18
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
XTAL C
0
/C
1
< 250
0V
VCON
3.3V
VCON=1.65V,
1.65V
150
100
5
+1
300
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
ppm/V
%
ppm
k
kHz
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/11/09 Page 3
Low Phase Noise VCXO (17MHz to 36MHz)
3. AC Electrical Specifications
PARAMETERS
Input Crystal Frequency
Output Clock Rise/Fall Time
Output Clock Duty Cycle
Output Enable/Disable Time
Start-Up Time
t
OE
t
SU
SYMBOL
F
in
t
r /
t
f
t
r /
t
f
CONDITIONS
Fundamental Mode
0.8V to 2.0V, 10 pF load
0.3V to 3.0V, 15 pF load
45
MIN.
17
1.15
3.7
50
5
1
55
TYP.
MAX.
36
UNITS
MHz
ns
%
ns
ms
4. Jitter and Phase Noise Specifications
PARAMETERS
RMS Period Jitter
(1 sigma – 1000 samples)
CONDITIONS
With capacitive decoupling between
V
DD
and GND.
27MHz @100Hz offset
Phase Noise,
Relative to Carrier
27MHz @1kHz offset
27MHz @10kHz offset
27MHz @100kHz offset
27MHz @1MHz offset
5. DC Specifications
PARAMETERS
Supply Current,
Dynamic
Supply Current,
Output Disabled
Operating Voltage
Output Low Voltage,CMOS
Output High Voltage, CMOS
Output Drive Current
VCXO Control Voltage
VCON
SYMBOL
I
DD
I
DD_OE
V
DD
V
OLC
V
OHC
I
OL
= +4mA
I
OH
= -4mA
For V
OL
<0.4V or V
OH
>2.4V
V
DD
– 0.4
8
0
9.5
V
DD
CONDITIONS
27MHz, 15pF Load, 3.3V
27MHz, 15pF Load, 2.5V
27MHz, 3.3V, OE=Low
27MHz, 2.5V, OE=Low
2.25
MIN.
TYP.
3.7
2.4
1.4
1
3.63
0.4
MAX.
5
3.5
UNITS
mA
mA
V
V
V
mA
V
MIN.
TYP.
2.5
-100
-125
-142
-150
-150
MAX.
UNITS
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/11/09 Page 4
Low Phase Noise VCXO (17MHz to 36MHz)
6. Crystal Specifications
PARAMETERS
Crystal Loading Rating (VCON = 1.65V, 3.3V Operation)
Crystal Loading Rating (VCON = 1.25V, 2.5V Operation)
Maximum Sustainable Drive Level
Operating Drive Level
Max C0
C0/C1
ESR
R
S
50
5
250
30
SYMBOL
C
L (xtal)
(see note
below)
MIN.
TYP.
7.8
8.9
200
MAX.
UNITS
pF
W
W
pF
-
Ω
Note:
The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range.
Note that the Cload values above are for the IC only, and do not include PCB parasitics. Crystal specifications for Cload include PCB parasitics.
PACKAGE INFORMATION (GREEN PACKAGE COMPLIANT)
SOP-8L
Symbol
A
A1
A2
B
C
D
E
H
L
e
SOT23-6 L
Symbol
A
A1
A2
b
c
D
E
H
L
e
Dimension in MM
Min.
Max.
1.05
1.35
0.05
0.15
1.00
1.20
0.30
0.50
0.08
0.20
2.80
3.00
1.50
1.70
2.60
3.0
0.35
0.55
0.95 BSC
Dimension in MM
Min.
Max.
1.35
1.75
0.10
0.25
1.25
1.50
0.33
0.53
0.19
0.27
4.80
5.00
3.80
4.00
5.80
6.20
0.40
0.89
1.27 BSC
E
H
D
A2 A
A1
e
b
C
L
Pin1 Dot
E
H
D
A2 A
A1
e
b
C
L
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/11/09 Page 5
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