1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC
FEATURES
Designed for PCB space savings with 3 low-power
Programmable PLLs and 3 distinct clock outputs.
Low-power consumption (<10µA when PDB is activated)
Output frequency:
o
<110MHz @ 1.8V operation
o
<166MHz @ 2.5V operation
o
<200MHz @ 3.3V operation
Input frequency:
o
Fundamental Crystal: 10MHz to 40MHz
o
Reference Input: 10MHz to 200MHz
Programmable I/O pins can be configured as Output
Enable (OE), Power Down (PDB) inputs, or Clock
output.
Disabled outputs programmable as HiZ or Active Low
Single 1.8V to 3.3V, ±10% power supply
Operating temperature range from -40C to 85C
Available in GREEN/RoHS compliant SOP-8L package.
DESCRIPTION
The PL613-05 is an advanced triple PLL design
based on PicoPLL, world’s smallest programmable
clock, technology. This flexible programmable
architecture is ideal for high performance, low-power,
low-cost applications. When using the power down
(PDB) feature the PL613-05 consumes less than 10
µA of power. Besides its small form factor and 3
distinct outputs that can reduce overall system costs,
the PL613-05 offers superior phase noise, jitter and
power consumption performance.
PIN CONFIGURATION
XIN, FIN
CLK2, OEM^, PDB^
VDD
CLK0
1
PL613-05
8
7
6
5
XOUT
VDD
CLK1
GND
2
3
4
SOP-8L
^ Deno tes internal pull up
BLOCK DIAGRAM
FREF
XIN/FIN
XOUT
OEM
Xtal
FREF
OSC
Odd/Even
Divider
(5-bits)
%1, %2,
%4, %8
Programmable
PLL1
VCO1
CLK1
Programming
Interface
Programmable
PLL2
VCO2
PDB
Odd/Even
Divider
(5-bits)
CLK0
FREF
Programmable
PLL3
VCO3
Odd/Even
Divider
(5-bits)
%1, %2,
%4, %8
CLK2, OEM, PDB
Programmable Function
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 09/16/11 Page 1
(Preliminary)
PL613-05
1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC
PACKAGE PIN ASSIGNMENT
Name
XIN, FIN
CLK2, OEM, PDB
VDD
CLK0
GND
CLK1
XOUT
Package
Pin #
1
2
3, 7
4
5
6
8
Type
I
B*
P
B*
P
O
O
Description
Crystal or Reference Clock input
- Programmable Clock (CLK2) output, or
- Output Enable Master (OEM) for all clock outputs, or
- Power Down mode (PDB) input
VDD connection
Programmable Clock (CLK0) output
GND connection
Programmable Clock (CLK1) output
Crystal output pin. Do Not Connect when using FIN
* Note:
All bidirectional buffers (I/Os) incorporate an internal 60KΩ pull up resistor except when PDB mode is used. In
configurations that use PDB, the PDB pin will have a 10MΩ pull up resistor.
KEY PROGRAMMING PARAM ETERS
CLK[ 0:2 ]
Output Frequency
CLK[0]
F
VCO2
/ P
CLK[1,2]
F
VCOx
/ (P*(1,2,4,8)) or
F
REF
/ (P*(1,2,4,8))
Where F
V CO
= F
REF
* M / R
M = 11 bit
R = 8 bit
P = 5 bit (Odd/Even Divider)
Output Drive Strength
Each output has three
optional drive strengths to
choose from. They are:
Low: 4mA
Std: 8mA (default)
High:16mA
Programmable Input/Output
Most pins are multi-function I/Os and can be
configured as:
OEM – (Master OE controlling all outputs)
PDB – (Power Down)
CLK[0:2] – (Output)
HiZ or Active Low disabled state
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 09/16/11 Page 2
(Preliminary)
PL613-05
1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC
FUNCTIONAL DESCRIPTION
The PL613-05 is a highly featured, very flexible, advanced triple PLL design for high performance, low-power
applications. The device accepts a low-cost fundamental crystal input of 10MHz to 40MHz or a reference clock
input of 10MHz to 200MHz and is capable of producing 3 distinct output frequencies up to 200MHz. All 3-PLLs are
fully programmable, with a total of four, 5-bit Post VCO, Odd/Even (patent pending) ‘P-counter’ dividers with
additional 1, 2, 4 or 8 ‘Post P-counter’ dividers to allow generating the most demanding frequencies easily. The
outputs can be programmed to deliver the generated frequencies from the PLLs, or the reference input. Each
bidirectional feature pin (I/O) on the PL613-05 incorporates a 60KΩ pull up resistor (10MΩ for PDB function) and
can be configured to perform various functions. Usage of various design features of these products is mentioned
in the following paragraphs.
PLL Programming
The three PLLs in PL613-05 are fully programmable.
Each PLL is equipped with an 8-bit input frequency
divider (R-Counter) and an 11-bit VCO frequency
feedback loop (M-Counter) divider. The three PLL
outputs are transferred to four 5-bit post VCO,
Odd/Even (patent pending) dividers (P-Counter), as
shown in the above diagrams . In addition, there are
three optional (÷1, ÷2, ÷4 or ÷8) post P-Counter
dividers, that can further divide the VCO frequencies.
In general, the PLL output frequency is determined by
the following formula
F
OUT
= (F
REF
*M) / (R*P)
For output calculations, please note that ‘P’ includes
the ‘P’ counter bits plus the additional optional (÷1,
÷2, ÷4 or ÷8) dividers, if used.
CLKx (Clock Outputs)
There are 3 distinct output frequencies available on
the PL613-05. Clock output frequencies can be
configured as follows:
CLK[0]
F
VCO 2
/ P
CLK[1,2]
F
VCO x
/ (P*(1,2,4,8)) or F
REF
/ (P*(1,2,4,8))
Each output can be programmed with a 4mA, 8mA, or
16mA drive strength. The maximum output frequency
is 200MHz @ 3.3V, 166MHz @ 2.5V or 1 10MHz @
1.8V.
1
OEM (Master Output Enable)
One pin can be configured to be a single Master OE
(OEM) input pin that controls all the outputs of th e
PL613-05. In addition the state of the disabled
outputs can be programmed to float (Hi Z) or Active
‘0’. The OEM pin incorporates a 60kΩ pull up
resistor for normal operating condition. The logic for
OEM is shown below:
OEM
OE Type
Osc PLL
Output
Pin
(Programmable)
0
0 (Default)
1
On
On
On
On
Hi Z
Active ‘0’
Normal Operation (Default)
Note: Typical enable time is 10ns.
Power-Down Control (PDB)
When activated, PDB ‘Disables all the PLLs, the
oscillator circuitry, counters, and all other active
circuitry. PDB activation disables all outputs and the
IC consumes <10µA of power. The PDB input
incorporates a 10MΩ pull up resistor for normal
operating condition.
The PDB feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode. The logic for PDB is shown below:
PDB
PDB Type
Osc
PLL
Output
Pin
Program
0
1
0 (Default)
1
Off
Off
Off
Off
Hi Z
Active ‘0’
Normal Operation (Default)
Note: Typical enable time is <2ms.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 09/16/11 Page 3
(Preliminary)
PL613-05
1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this
equals ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like
ringing).
- Design long traces (<1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections
bouncing back and forth.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
(Typical buffer impedance 20Ω)
To CMOS Input
50Ω line
Cst
XIN
1
Cpt
8
Cpt
XOUT
Decoupling and Power Supply Considerations
- Place decoupling capacitors as close as possible to
the V
DD
pin(s) to limit noise from the power supply
- Multiple V
DD
pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with V
DD
can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1
F
for
designs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
Crystal Tuning Circuit
Series and parallel capacitors used to fine tune the crystal load to the circuit load.
Crystal
Series Resistor
Use value to match output buffer impedance to
50Ω trace. Typical value 30Ω
CST
– Series Capacitor, used to lower circuit load to match crystal load. Raises frequency offset.
This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator.
CPT
– Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers
frequency offset.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 09/16/11 Page 4
(Preliminary)
PL613-05
1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature (Green package)
Data Retention @ 85C
Storage Temperature
Ambient Operating Temperature*
T
S
10
-65
-40
150
85
SYMBOL
V
DD
V
I
V
O
MIN.
-0.5
-0.5
-0.5
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
260
UNITS
V
V
V
C
Year
C
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency (XIN)
Input (FIN) Frequency
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
@ V
DD
=3.3V
@ V
DD
=2.5V
@ V
DD
=1.8V
Internally AC coupled (High Frequency)
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ V
DD
=3.3V
Output Frequency
Settling Time
Output Enable Time
VDD Sensitivity
Output Rise Time
Output Fall Time
Duty Cycle
Period Jitter, Pk-to-Pk*
(10,000 samples)
@ V
DD
=2.5V
@ V
DD
=1.8V
At power-up (after V
DD
increases over 1.62V)
OE Function; Ta=25º C, 15pF Load
PDB Function; Ta=25º C, 15pF Load
Frequency vs. V
DD
+/-10%
15pF Load, 10/90% V
DD
, High Drive, 3.3V
15pF Load, 90/10% V
DD
, High Drive, 3.3V
PLL Enabled, @ V
DD
/2, High Drive
Configuration Dependant, with capacitive
decoupling between V
DD
and GND.
45
-2
1.2
1.2
50
300
0.9
0.1
10
CONDITIONS
Fundamental Crystal
MIN.
10
TYP.
MAX.
40
200
166
110
V
DD
V
DD
200
166
110
2
10
2
2
1.7
1.7
55
ms
ns
ms
ppm
ns
ns
%
ps
MHz
Vpp
Vpp
MHz
UNITS
MHz
* Note: Jitter perform ance depends on the programming parameters.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
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