SiC734CD9
New Product
Vishay Siliconix
Fast Switching MOSFETs With Integrated Driver
PRODUCT SUMMARY
Input Voltage Range
Output Voltage Range
Operating Frequency
Continuous Output Current
Peak Efficiency
Optimized Duty Cycle Ratio
3.3 to 20 V
0.5 to 6 V
100 kHz to 1 MHz
Up to 25 A
92.8
10 %
PowerPAK MLF 9 x 9
FEATURES
• Low-side MOSFET control pin for
pre-bias start-up
• Undervoltage Lockout for safe operation
RoHS
• Internal boostrap diode reduces
COMPLIANT
component count
• Break-Before-Make operation
• Turn-on/Turn-off Capability
• Compatible with any single or multi-phase PWM
controller
• Low profile, thermally enhanced PowerPAK
®
MLF
9 x 9 Package
APPLICATIONS
• DC-to-DC Point-of-Load Converters
- 3.3 V, 5 V, or 12 V Intermediate BUS
- Examples
- 12 V
IN
/ 0.8 - 2.5 V
OUT
- 5 V
IN
/ 0.8 - 1.5 V
OUT
• Servers and Computers
• Single and Multi-Phase Conversion
Bottom
View
Ordering Information: SiC734CD9-T1-E3 (Lead (Pb)–free)
* see page 2 for peak temperature
DESCRIPTION
The SiC734CD9 is an integrated solution which con-
tains two PWM-optimized MOSFETs (high side and
low side MOSFETs) and a driver IC. Integrating the
driver allows better optimization of Power MOSFETs.
This minimizes the losses and provides better perfor-
FUNCTIONAL BLOCK DIAGRAM
mance at higher frequency. The SiC734CD9 is packed
in Vishay Siliconix’s high performance PowerPAK MLF
9 x 9 package. Compact co-packing of components
helps to reduce stray inductance, and hence increases
efficiency.
V
DD
C
BOOT
V
IN
UVLO
SHDN
+
-
BBM
SW
V
DD
PWM
SYNC
CGND
PGND
Figure 1.
Document Number: 73672
S-61011–Rev. B, 12-Jun-06
www.vishay.com
1
SiC734CD9
Vishay Siliconix
New Product
ABSOLUTE MAXIMUM RATINGS
T
A
= 25 °C, unless otherwise noted
Parameter
Logic Supply
Logic Inputs
Common Switch Node
Drain Voltage
Bootstrap Voltage
Maximum Power Sissipation (Measured at 25 °C )
Operating Juncyion and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
a, b
Symbol
V
DD
V
PWM
V
SW
V
IN
C
BOOT
P
D
T
j
, T
stg
Steady State
7
7.3
30
30
SW + 7
6
- 65 to 125
245
°C
W
V
Unit
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Drain Voltage
Logic Supply
Input Logic PWM Voltage
Bootstrap Capacitor
Symbol
V
IN
V
DD
V
PWM
C
BOOT
Steady State
3.3 to 20
4.5 to 5.5
5
100 n to 1µ
Unit
V
F
THERMAL RESISTANCE RATINGS
Parameter
c
Maximum Junction-to-Case
Maximum Junction-to-Ambient
(PCB = Copper 25 mm x 25 mm)
Symbol
R
thJC
R
thJA
Typical
3.5
60
Maximum
4.5
75
Unit
°C/W
Steady State
Notes:
a. See Reliability Manual for profile. The PowerPAK MLF 9 x 9 is a leadless package. The end of the lead terminal is exposed copper (not plated)
as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot guaranteed and is not required to ensure
adequate bottom side soldering interconnection.
b. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
c. Junction-to-case thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use
in conjunction with the thermal impedance of the PC board pads to ambient (R
thJA
= R
thJC
+ R
thPCB-A
). It can also be used to estimate chip
temperature if power dissipation and the lead temperature of heat carrying (drain) lead is known.
www.vishay.com
2
Document Number: 73672
S-61011–Rev. B, 12-Jun-06
SiC734CD9
New Product
Vishay Siliconix
SPECIFICATIONS
Test Condition Unless Specified
T
A
= 25 °C
4.5 V < V
DD
< 5.5 V, 4.5 V < V
IN
< 20 V
Limits
Min
Typ
a
Max
Unit
Parameter
Controller
Logic Voltage
Logic Current (Static)
Logic Current (Dynamic)
Symbol
V
DD
I
DD(EN)
I
DD(DIS)
I
DD1(DYN)
I
DD2(DYN)
4.5
V
DD
= 4.5 V, SYNC = H, PWM = H, SHDN = H
V
DD
= 4.5 V, SYNC = H, PWM = H, SHDN = L
V
DD
= 5 V, f
PWM
= 250 kHz
c
V
DD
= 5 V, f
PWM
= 700 kHz
c
2.5
1185
115
24
5.5
V
µA
mA
52
Logic Input
Logic Input (VPWM)
Logic Input Voltage (V
SYNC
)
Logic Input Voltage (V
SHDN
)
Input Voltage Hysteresis (PWM)
Logic Input Current
Protection
Break-Before-Make Reference
Under-Voltage Lockout
Under-Voltage Lockout Hysteresis
MOSFETs
Drain-Source Voltage
Drain-Source On-State
Resistance
a
Diode Forward Voltage
a
Dynamic
b, c
Turn On Delay Time
Turn Off Delay Time
t
d(on)
t
d(off)
50 % - 50 %
c
58
31
ns
V
DS
r
DS(on)1
r
DS(on)2
V
SD1
V
SD2
I
D
= 250 µA
V
DD
= 5 V, I
D
= 10 A
T
A
= 25 °C
I
S
= 2 A, V
GS
= 0 V
High-Side
Low-Side
High-Side
Low-Side
30
32
9.5
3.7
0.7
0.67
12.3
4.5
1.1
1.1
mΩ
V
V
V
BBM
V
UVLO
V
H
V
DD
= 5.5 V
V
DD
= 5 V, SYNC = H, SHDN = H
3.5
2.4
4.1
0.4
4.25
V
High
Low
V
PWMH
V
PWML
V
SYNC
V
SHDN
V
HYS
I
SHDN
I
PWM
V
DD
= 5.5 V, SHDN = 0 V
V
DD
= 5.5 V, PMW = 5.5 V
V
DD
= 5 V, SYNC = H, SHDN = H
V
DD
= 5 V, PMW = H, SHDN = H
V
DD
= 5 V, PMW = H, SYNC = H
1.35
2.0
2.0
400
117
114
mV
µA
V
Notes:
a) Pulse test; pulse width
≤
300 ms, duty cycle
≤
2 %.
b) Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c) Using application board SiDB766706.
Document Number: 73672
S-61011–Rev. B, 12-Jun-06
www.vishay.com
3
SiC734CD9
Vishay Siliconix
TIMING DIAGRAM
SHDN
SYNC
PWM
HS MOSFET
Gate
LS MOSFET
Gate
SW
t
d(on)
t
d(off)
New Product
Figure 2
APPLICATION INFORMATION
a
(25 °C, unless noted, LFM = 0)
96
94
92
90
88
300 kHz
86
84
700 kHz
82
80
3
5
7
9
11
13
15
17
19
21
23
25
Output Current – (A)
1
0
3
5
7
9
11
13
15
17
19
21
23
25
Output Current – (A)
500 kHz
Total Loss (
W
)
Efficiency (
%
)
7
6
700 kHz
5
500 kHz
4
300 kHz
3
2
Figure 3. Total Efficiency 12 V
IN
/1.3 V
OUT
Notes:
a) Experimental results using an evaluation board with a specific set of operating conditions.
Figure 4. Total Loss 12 V
IN
/1.3 V
OUT
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Document Number: 73672
S-61011–Rev. B, 12-Jun-06
SiC734CD9
New Product
PIN CONFIGURATION
PowerPAK MLF 9 mm 9 mm (Bottom View)
Vishay Siliconix
S
W
S
W
S
W
S
W
S
W
V
I
N
30
27
2
8
29
31
25
V
I
N
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
24
23
22
21
20
19
18
17
CGND
(SW)
V
IN
Driver
Tab
Low-Side
MOS Tab
High-Side
MOS Tab
26
32
V
I
N
1
2
3
V
IN
V
IN
V
IN
4
5
6
7
8
V
IN
CGND
C
Boot
C
Boot
V
DD
11
9
16
PG
N
D
15
PG
N
D
14
SHD
N
13
SY
N
C
12
CG
N
D
10
V
DD
V
DD
P
W
M
TRUTH TABLE
SHDN
L
H
H
H
H
SYNC
X
L
L
H
H
PWM
X
L
H
L
H
HS MOSFET
OFF
OFF
ON
OFF
ON
LS MOSFET
OFF
OFF
OFF
ON
OFF
PIN DESCRIPTION
Pin Number
1 - 4, 30 - 32
5, 12
6, 7
8, 9, 10
11
13
14
15 - 24
25 - 29
Symbol
V
IN
CGND
C
BOOT
V
DD
PMW
SYNC
SHDN
PGND
SW
Description
Input-Voltage (High-Side MOSFET Drain)
Control Ground. Should be connected to PGND externally
Connection pin for Bootstrap Capacitor for High-Side MOSFET
Logic Supply Voltage - decoupling to GND with a CAP is strongly recommended
Pulse Width Modulation (PWM) Signal Input
Disable Low-Side MOSFET Drive
Disable All Functions (Active Low)
Power Ground (Low-Side MOSFET Source)
Connection Pin for Output Inductor (High-Side MOSFET Source/Low-Side MOSFET Drain)
Document Number: 73672
S-61011–Rev. B, 12-Jun-06
www.vishay.com
5
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