SUMMIT
MICROELECTRONICS, Inc.
SMH4042A
Distributed Power Hot-Swap Controller for
CompactPCI
FEATURES
Full Voltage Control for Hot Swap Applications
15V High Side Driver Generation Allows use
of Low On Resistance N-Channel FETs
Under-Voltage Lockout
Electronic Circuit Breakers
Card Insertion Detection
Host V
CC
Detection
Card Voltage Sequencing
Flexible Reset Control
Low Voltage Resets
Host Reset Filtering
Soft Reset
Adjustable Power On Slew Rate
Suppoprts Mixed Voltage Cards
Two Wire I
2
C Serial Data Interface
4k-Bit E
2
PROM Memory
FUNCTIONAL BLOCK DIAGRAM
28
VCC
BD_SEL1#
BD_SEL2#
3
8
10
11
19
18
24
ISLEW
A0
A1
A2
SCL
SDA
–
13
12
1VREF
VGATE3
EEPROM
Memory
Array
VGATE5
5
22
27
CBI_3
LOCAL_PCI_RST
LOCAL_PCI_RST#
20
9
+
–
23
HST_3V_MON
+
–
21
CARD_3V_MON
25
CARD_5V_MON
+
–
1.25V
7
17
6
PWR_EN
PCI_RST#
VSEL
GND
14
©SUMMIT MICROELECTRONICS, Inc., 2005 • 1717 Fox Drive, San Jose, CA 95131 • Phone 408-436-9890 • FAX 408-436-9897 •
www.summitmicro.com
Characteristics subject to change without notice
+
+
–
–
1
CBI_5
+
SGNL_VLD#
CONTROL
ASSOCIATE
MEMBER
16
HEALTHY#
15
DRVREN#
2
FAULT#
4
2070 9.2 10/21/05
1
SMH4042A
DESCRIPTION
The SMH4042A is a fully integrated hot swap controller that
provides complete power control for add-in cards ranging in
use for basic hot swap systems to high availability
CompactPCI
systems. It detects proper insertion of the
card and senses valid supply voltage levels at the
backplane. Utilizing external low on-resistance N-channel
MOSFETs, card power is ramped by two high-side driver
outputs that are slew-rate limited at 250V/s.
The SMH4042A continuously monitors the host supplies,
the add-in card supplies and the add-in card current. If
the SMH4042A detects the current is higher than the
programmed value it will shut down the MOSFETs and
issue a fault status back to the host.
The internal 512
×
8 E
2
PROM can be used as configuration
memory for the individual card or as general purpose
memory. The proprietary Data Download mode provides
a more direct interface to the E
2
PROM, simplifying
access by the add-in card’s controller or ASIC.
Programming of configuration, control and calibration
values by the user can be simplified with the interface
adapter and Windows GUI software obtainable from
Summit Microelectronics.
PIN CONFIGURATION
CBI_5
DRVREN#
ISLEW
FAULT#
1VREF
VSEL
PWR_EN
A0
LOCAL_PCI_RST#
A1
A2
BD_SEL2#
BD_SEL1#
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
VGATE5
nc
CARD_5V_MON
CBI_3
HST_3V_MON
VGATE3
CARD_3V_MON
LOCAL_PCI_RST
SCL
SDA
PCI_RST#
SGNL_VLD#
HEALTHY#
2070 PCon
2
2070 9.2 10/21/05
SUMMIT MICROELECTRONICS, Inc.
SMH4042A
PIN DESCRIPTIONS
A0 (8)
Address 0 is not used by the memory array. It can be
connected to ground or left floating. It must not be
connected V
CC
.
A1, A2 (10, 11)
Address inputs 1 and 2 are used to set the two-bit device
address of the memory array. The state of these inputs
will determine the device address for the memory if it is
on a two-wire bus with multiple memories with the same
device type identifier.
SCL (19)
The SCL input is used to clock data into and out of the
memory array. In the write mode, data must remain stable
while SCL is HIGH. In the read mode, data is clocked out
on the falling edge of SCL.
SDA (18)
The SDA pin is a bidirectional pin used to transfer data into
and out of the memory array. Data changing from one
state to the other may occur only when SCL is LOW,
except when generating START or STOP conditions.
SDA is an open-drain output and may be wire-ORed with
any number of open-drain outputs.
CARD_3V_MON (21)
This input monitors the card-side 3.3V supply. If the input
falls below V
TRIP
then the HEALTHY# and SGNL_VLD#
outputs are de-asserted and the reset outputs are driven
active.
CARD_5V_MON (25)
This input monitors the card-side 5V supply. If the input
falls below V
TRIP
then the HEALTHY# and SGNL_VLD#
outputs are de-asserted and the reset outputs are driven
active.
CBI_3 (24)
CBI_3 is the circuit breaker input for the low supply. With
a series resistor placed in the supply path between VCC3
and CBI_3, the circuit breaker will trip whenever the
voltage across the resistor exceeds 50mV.
CBI_5 (1)
CBI_5 is the circuit breaker input for the supply voltage.
With a series resistor placed in the supply path between
the 5V early power and CBI_5, the circuit breaker will trip
whenever the voltage across the resistor exceeds 50mV.
HST_3V_MON (23)
This input monitors the host 3.3V supply and it is used as
a reference for the circuit breaker comparator. If VCC3
falls below V
TRIP
then SGNL_VLD# is de-asserted, the
high side drivers are disabled, and LOCAL_PCI_RST# is
asserted.
ISLEW (3)
A Diode-connected NFET input. It may be used to adjust
the 250V/s default slew rate of the high-side driver
outputs.
PCI_RST# (17)
A TTL level reset input signal from the host interface. A
high to low transition (held low longer than 40ns) will
initiate a reset sequence. The LOCAL_PCI_RST# and
LOCAL_PCI_RST outputs will be driven active for a
minimum period of t
PURST
. If the PCI_RST# input is still
held low after t
PURST
times out the reset outputs will
continue to be driven until PCI_RST# is released.
PWR_EN (7)
A TTL level input that allows the host to enable or disable
the power to the individual card. During initial power up
this signal would start in a low state, and then be driven
high during software initialization. If this signal is driven
low then the power supply control outputs will be driven
into the inactive state and the reset signals asserted. In
a “non-High Availability” system this input can be tied
high. The PWR_EN input is also used to reset the
SMH4042A circuit breakers. After an over-current condi-
tion is detected the VGATE outputs can be turned back
on by first taking PWR_EN low then returning it high.
VSEL (6)
A TTL level input used to determine which of the host
power supply inputs will be monitored for valid voltage and
reset generation. This is a static input and the pin should
be tied to V
CC
or ground through a resistor. VSEL is high
for 3.3V power. VSEL is low for 5V or mixed mode power.
V
CC
(28)
The power supply input. It is monitored for power integrity.
If it falls below the 5V sense threshold (V
TRIP
) and the
VSEL input is low then the SGNL_VLD# and HEALTHY#
signals are de-asserted, the high side drivers disabled,
and reset outputs asserted. On a
CompactPCI
board this
must be connected to early power.
SUMMIT MICROELECTRONICS, Inc.
2070 9.2 10/21/05
3
SMH4042A
GND (14)
Power supply return line. Ground should be applied at the
same time as early power.
BD_SEL1#, BD_SEL2# (13, 12)
These are active low TTL level inputs with internal pull-
ups to V
CC
. When pulled low they indicate full board
insertion. On the host side the signals should be directly
tied to ground. In a “High Availability” application these
inputs can be the last pins to mate with the backplane.
Alternatively, they can be actively driven by the host, or
be connected to switches interfaced to the board ejectors,
or any combination. Regardless, both inputs must be low
before the SMH4042A will begin to turn on the backend
voltage.
DRVREN# (2)
An open-drain, active-low output that indicates the status
of the 3 volt and 5 volt high side driver outputs (VGATE5
and VGATE3). This signal may also be used as a
switching signal for the 12 volt supply.
FAULT# (4)
An open-drain, active-low output. It will be driven low
whenever an over-current condition is detected. It will be
reset at the same time that the VGATE outputs are turned
back on after a reset from the host on the PWR_EN signal.
HEALTHY# (15)
An open-drain, active-low output indicating card side
power inputs are above their reset trip levels.
LOCAL_PCI_RST# (9)
An open-drain active-low output. It is used to reset the
backend circuitry on the add-in card. It is active whenever
the card-side monitor inputs are below their respective
V
TRIP
levels. It may also be driven low by a low input on
the PCI_RST# pin.
LOCAL_PCI_RST (20)
An open-drain (PFET) active-high output. It operates in
parallel with LOCAL_PCI_RST#, providing an active high
reset signal which is required by many 8051 style MCUs.
It is active whenever the card-side monitor inputs are
below their respective V
TRIP
levels. It may also be driven
active by a low input on the PCI_RST# pin.
SGNL_VLD# (16)
An open-drain, active-low output that indicates card side
power is valid and the internal card side PCI_RST# timer
has timed out.
VGATE3 (22)
A slew rate limited high side driver output for the 3.3V
external power FET gate. The output-voltage is generated
by an on-board charge pump.
VGATE5 (27)
A slew rate limited high side driver output for the 5V
external power FET gate. The output voltage is generated
by an on-board charge pump.
1V
REF
(5)
This output provides a 1V reference for pre-charging the
bus signal pins. Implementing a simple unity-gain ampli-
fier circuit will allow pre-charging a large number of pins.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ......................... –55°C to 125°C
Storage Temperature .............................. –65°C to 150°C
Lead Solder Temperature (10 secs) ..................... 300 °C
Terminal Voltage with Respect to GND:
CARD_3V_MON, CARD_5V_MON,
HST_3V_MON, SGNL_VLD#, HEALTHY#,
LOCAL_PCI_RET#, V
CC ........................................
7V
VGATE3, VGATE5, DRVREN# .................. 16V
RESET ............................................ V
CC
+ 0.7V
All Others ........................................ V
CC
+ 0.7V
Junction Temperature..........................................150°C
ESD Rating per JEDEC……………………………..2000V
Latch-Up testing per JEDEC………………......+/- 100mA
RECOMMENDED OPERATING CONDITIONS
*
Temperature Range (Industrial)...……....-40° C to +85°C
(Commercial)...……....-5° C to +70°C
Supply Voltage………………….....….………2.7V to 5.5V
Package Thermal Resistance (θ JA)
28 Lead SOIC/SSOP...…………………………80
o
C/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020. MSL
3 for 100% Sn, RoHS compliant, see ordering information
RELIABILITY CHARACTERISTICS
Data Retention……………………………..…..100 Years
Endurance……………………….……….100,000 Cycles
Note * - The device is not guaranteed to function outside its operating
rating. Stresses listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is
not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
SUMMIT MICROELECTRONICS, Inc.
4
2070 9.2 10/21/05
SMH4042A
DC OPERATING CHARACTERISTICS
(Over
Recommended Operating Conditions; Voltages are relative to GND)
Symbol
V
CC
I
CC1
I
CC2
Parameter
Supply voltage
Power Supply Current
(1)
Conditions
(2)
Min.
1
Typ.
Max.
Units
V
Operating
Writing
V
CC
5
A
V
CC
5
B
HST_3V_MON
G
HST_3V_MON
H
HST_3V_MON
K
HST_3V_MON
L
CARD_5V_MON
M
CARD_5V_MON
N
CARD_3V_MON
M
CARD_3V_MON
N
4.250
4.500
2.57
2.72
2.87
3.00
4.375
4.625
2.65
2.80
2.95
3.10
V
CC
5 + 50mV
V
CC
5 – 50mV
HST_3V_MON +
50mV
HST_3V_MON –
50mV
7
500
3
4.500
4.750
2.72
2.87
3.00
3.17
µA
mA
V
V
V
V
V
V
V
V
V
V
mV
V
TRIP
(2) Threshold Levels
V
TRHYST
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
V
OLRS
V
OHRS
V
OHVG3
V
OHVG5
V
REF
V
CB
Notes:
T ip Point Hysteresis
r
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
LOCAL_PCI_RST# Low
RESET High
VGATE3 High
VGATE5 High
Reference Output V ltage
o
V
CC
= 5.0V I
OL
= 2.1mA
,
V
CC
= 5.0V I
OH
= –400µA
,
I
OL
= 3.2mA
I
OH
= –800µA
I
OH
= 5µA
I
OH
= 5µA
No Load
V
CC
– 0.75V
12
13
0.95
40
2.4
–0.1
2
2
10
0.8
V
CC
+ 1V
0.4
µA
µA
V
V
V
V
0.4
V
V
13
14
1.00
50
15
15
1.05
60
V
V
V
mV
Circuit Breaker T ip V ltage (3)
r
o
2037 Elect Table 2.0
(1) The SMH4042A will drive the Reset outputs and voltage control signals throughout the operating range of 1V to 5.5V. The balance
of the logic will not be guaranteed operational unless V
CC
is greater than 2.7V.
(2) A, B,G, H, K. L, M, & N refer to the Part Number Suffix.
(3) For T
A
= –10ºC to 85ºC.
SUMMIT MICROELECTRONICS, Inc.
2070 9.2 10/21/05
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
