To all our customers
Regarding the change of names mentioned in the document, such as
Hitachi Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were
transferred to Renesas Technology Corporation on April 1st 2003.
These operations include microcomputer, logic, analog and discrete devices,
and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors,
and other Hitachi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp.
Thank you for your understanding. Except for our corporate trademark,
logo and corporate statement, no changes whatsoever have been made to the
contents of the document, and these changes do not constitute any alteration
to the contents of the document itself.
Renesas Technology Home Page: www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Renesas Technology Corp.
OMC942723157
H8/3614 Series
H8/3614
HD6473614, HD6433614
H8/3613
HD6433613
H8/3612
HD6433612
Hardware Manual
Preface
The H8/3614 Series of single-chip microcomputers has an H8/300L CPU core and a variety of
peripheral functions needed in system configurations.
This manual describes the CPU architecture, peripheral functions, electrical characteristics, and
package dimensions of the H8/3614 Series.
Refer to the H8/300L Series Programming Manual (ADE-602-040) for a detailed description of the
instruction set.
Contents
Section 1
1.1
1.2
1.3
Overview
..........................................................................................................
Overview.........................................................................................................................
Internal Block Diagram ..................................................................................................
Pin Arrangement and Functions .....................................................................................
1.3.1 Pin Arrangement.................................................................................................
1.3.2 Pin Functions ......................................................................................................
1
1
5
7
7
11
Section 2
2.1
CPU
................................................................................................................... 15
15
15
16
17
18
18
18
20
20
21
22
23
23
25
29
31
33
34
34
36
40
42
43
45
45
46
46
46
47
47
48
49
49
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Overview.........................................................................................................................
2.1.1 Features...............................................................................................................
2.1.2 Address Space.....................................................................................................
2.1.3 Register Configuration........................................................................................
Register Descriptions......................................................................................................
2.2.1 General Registers................................................................................................
2.2.2 Control Registers ................................................................................................
2.2.3 Initial Register Values ........................................................................................
Data Formats...................................................................................................................
2.3.1 Data Formats in General Registers .....................................................................
2.3.2 Memory Data Formats........................................................................................
Addressing Modes ..........................................................................................................
2.4.1 Addressing Modes ..............................................................................................
2.4.2 Effective Address Calculation ............................................................................
Instruction Set.................................................................................................................
2.5.1 Data Transfer Instructions ..................................................................................
2.5.2 Arithmetic Operations ........................................................................................
2.5.3 Logic Operations ................................................................................................
2.5.4 Shift Operations ..................................................................................................
2.5.5 Bit Manipulations ...............................................................................................
2.5.6 Branching Instructions........................................................................................
2.5.7 System Control Instructions ...............................................................................
2.5.8 Block Data Transfer Instruction .........................................................................
CPU States ......................................................................................................................
2.6.1 Overview.............................................................................................................
2.6.2 Program Execution State ....................................................................................
2.6.3 Program Halt State..............................................................................................
2.6.4 Exception-Handling States .................................................................................
Basic Operation Timing..................................................................................................
2.7.1 Access to On-Chip Memory (RAM, ROM) .......................................................
2.7.2 Access to On-Chip Peripheral Modules .............................................................
Application Notes ...........................................................................................................
2.8.1 Notes on Data Access .........................................................................................
2.8.2
Notes on Bit Manipulation.................................................................................. 51
Section 3
3.1
3.2
System Control
.............................................................................................. 55
55
55
55
56
58
66
67
67
72
72
73
74
74
75
75
77
77
77
78
79
81
82
82
84
3.3
3.4
Overview.........................................................................................................................
Exception Handling ........................................................................................................
3.2.1 Reset ...................................................................................................................
3.2.2 Interrupts.............................................................................................................
3.2.3 Interrupt Control Registers .................................................................................
3.2.4 External Interrupts ..............................................................................................
3.2.5 Internal Interrupts ...............................................................................................
3.2.6 Interrupt Operations............................................................................................
3.2.7 Return from an Interrupt.....................................................................................
3.2.8 Interrupt Response Time.....................................................................................
3.2.9 Valid Interrupts in Each Mode ...........................................................................
3.2.10 Notes on Stack Area Use ....................................................................................
3.2.11 Note on Clearing Interrupt Request Registers ....................................................
System Modes.................................................................................................................
3.3.1 Overview.............................................................................................................
3.3.2 Active Mode .......................................................................................................
3.3.3 Sleep Mode .........................................................................................................
3.3.4 Standby Mode.....................................................................................................
3.3.5 Watch Mode........................................................................................................
3.3.6 Subactive Mode ..................................................................................................
3.3.7 Application Notes ...............................................................................................
System Control Registers ...............................................................................................
3.4.1 System Control Register 1 (SYSCR1)................................................................
3.4.2 System Control Register 2 (SYSCR2)................................................................
Section 4
4.1
4.2
4.3
Clock Pulse Generators
............................................................................... 85
85
85
86
89
Overview.........................................................................................................................
4.1.1 Block Diagram....................................................................................................
System Clock Generator .................................................................................................
Subclock Generator ........................................................................................................
Section 5
5.1
I/O Ports
........................................................................................................... 91
91
93
94
95
95
95
96
96
5.2
Overview.........................................................................................................................
5.1.1 Port Types and Mask Options.............................................................................
5.1.2 Pull-Up MOS ......................................................................................................
Port 0 ............................................................................................................................
5.2.1 Overview.............................................................................................................
5.2.2 Register Configuration and Description .............................................................
5.2.3 Pin Functions ......................................................................................................
5.2.4 Pin States ............................................................................................................
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