HY5V52CF
4 Banks x 2M x 32Bit Synchronous DRAM
Document Title
4Banks x 2M x 32Bit Synchronous DRAM
Revision History
Revision No.
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Initial Draft
2nd Generation
133MHz Speed Added
Changed IDD Spec.
Changed Package Size
166MHz Speed Added
Defined Input/Output Cap. Spec.
History
Draft Date
Sep.06.2002
Nov.11.2002
Dec.13.2002
June.27.2003
July.14.2003
Aug. 06.2003
Dec. 05.2003
Remark
Preliminary
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.7 / Dec. 2003
HY5V52CF
4 Banks x 2M x 32Bit Synchronous DRAM
DESCRIPTION
Preliminary
The Hynix HY5V52CF is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applications
which require wide data I/O and high bandwidth. HY5V52CF is organized as 4banks of 2,097,152x32.
HY5V52CF is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
•
•
•
•
JEDEC standard 3.3V power supply
All device pins are compatible with LVTTL interface
90Ball FBGA with 0.8mm of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM0,1,2 and 3
•
•
Internal four banks operation
•
Burst Read Single Write operation
Programmable CAS Latency ; 2, 3 Clocks
•
•
•
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
ORDERING INFORMATION
Part No.
HY5V52C(L)F-6
HY5V52C(L)F-H
HY5V52C(L)F-8
HY5V52C(L)F-P
HY5V52C(L)F-S
Clock Frequency
166MHz
133MHz
125MHz
100MHz
100MHz
Organization
Interface
Package
4Banks x 2Mbits x32
LVTTL
90Ball FBGA
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.7 / Dec. 2003
HY5V52CF
Ball CONFIGURATION
1
A
D Q 26
D Q 24
VSS
VDD
DQ 23
D Q 21
2
3
4
5
6
7
8
9
B
D Q 28
VDDQ
VSSQ
VDDQ
VSSQ
D Q 19
C
VSSQ
D Q 27
DQ 25
D Q 22
DQ 20
VDDQ
D
VSSQ
D Q 29
DQ 30
D Q 17
DQ 18
VDDQ
E
VDDQ
D Q 31
NC
NC
DQ 16
VSSQ
F
VSS
DQM3
A3
A2
DQM2
VDD
G
A4
A5
A6
A10
A0
A1
H
A7
A8
NC
T o p V ie w
NC
BA1
A 11
J
C LK
CKE
A9
BA0
/C S
/R A S
K
DQM1
NC
NC
/C A S
/W E
DQM0
L
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
M
VSSQ
D Q 10
DQ9
DQ6
DQ5
VDDQ
N
VSSQ
D Q 12
DQ 14
DQ1
DQ3
VDDQ
P
DQ 11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
R
DQ 13
D Q 15
VSS
VDD
DQ0
DQ2
Ball DESCRIPTION
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A11
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe, Write
Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the rising edge
of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one of the states
among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Rev. 0.7 / Dec. 2003
3
HY5V52CF
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks X 32 I/O Synchronous DRAM
Self Refresh Logic
& Timer
Refresh
Counter
CLK
CKE
CS
State Machine
RAS
CAS
WE
DQM0
DQM1
DQM2
DQM3
Row Active
Row
Pre
Decoder
2Mx32 Bank 3
2Mx32 Bank 2
2Mx32 Bank 1
2Mx32 Bank 0
DQ0
DQ1
I/O Buffer & Logic
X decoder
Sense AMP & I/O Gate
X decoder
X decoder
X decoder
Memory
Cell
Array
Column Active
Column
Pre
Decoder
Y decoder
DQ30
DQ31
Bank Select
Address
Register
Column Add
Counter
A0
A1
Address Buffers
Burst
Counter
A12
BA0
BA1
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
Rev. 0.7 / Dec. 2003
4
HY5V52CF
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Short Circuit Output Current
Power Dissipation
Soldering Temperature
⋅
Time
T
A
T
STG
V
IN
, V
OUT
V
DD,
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
1
260
⋅
10
Rating
°C
°C
V
V
mA
W
°C ⋅
Sec
Unit
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION
(TA=0 to 70°C)
Parameter
Power Supply Voltage
Input high voltage
Input low voltage
Symbol
V
DD
, V
DDQ
V
IH
V
IL
Min
3.135
2.0
V
SSQ
- 0.3
Typ.
3.3
3.0
0
Max
3.6
V
DDQ
+ 0.3
0.8
Unit
V
V
V
Note
1
1,2
1,3
Note :
1.All voltages are referenced to V
SS
= 0V
2.V
IH
(max) is acceptable 5.6V AC pulse width with
≤3ns
of duration with no input clamp diodes
3.V
IL
(min) is acceptable -2.0V AC pulse width with
≤3ns
of duration with no input clamp diodes
AC OPERATING CONDITION
(TA=0 to 70°C, 3.0V
≤V
DD
≤3.6V,
V
SS
=0V - Note1)
Parameter
AC input high / low level voltage
Input timing measurement reference level voltage
Input rise / fall time
Output timing measurement reference level
Output load capacitance for access time measurement
Symbol
V
IH
/ V
IL
Vtrip
tR / tF
Voutref
CL
Value
2.4/0.4
1.4
1
1.4
30
Unit
V
V
ns
V
pF
1
Note
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)
For details, refer to AC/DC output load circuit
Rev. 0.7 / Dec. 2003
5
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