D2
PA
K
BUK6C2R1-55C
N-channel TrenchMOS intermediate level FET
Rev. 3 — 18 January 2012
Product data sheet
1. Product profile
1.1 General description
Intermediate level gate drive N-channel enhancement mode Field-Effect Transistor (FET)
in a plastic package using TrenchMOS technology. This product has been designed and
qualified to the appropriate AEC standard for use in high-performance automotive
applications.
1.2 Features and benefits
AEC Q101 compliant
High current handling capability, up to
320 A
Low conduction losses due to very low
on-state resistance
Suitable for standard and logic level
gate drive sources
Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
12 V automotive systems
Electric and electro-hydraulic power
steering
Motors, lamps and solenoids
Start-Stop micro-hybrid applications
Transmission control
Ultra high performance power
switching
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
drain-source on-state
resistance
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
V
GS
= 10 V; T
mb
= 25 °C;
see
Figure 1
T
mb
= 25 °C; see
Figure 2
V
GS
= 10 V; I
D
= 90 A;
T
j
= 25 °C;
see
Figure 11
Min
-
-
-
-
Typ
-
-
-
1.9
Max
55
228
300
2.3
Unit
V
A
W
mΩ
Static characteristics
NXP Semiconductors
BUK6C2R1-55C
N-channel TrenchMOS intermediate level FET
Quick reference data
…continued
Parameter
gate-drain charge
Conditions
I
D
= 180 A; V
DS
= 44 V;
V
GS
= 10 V;
see
Figure 13;
see
Figure 14
I
D
= 120 A; V
sup
≤
55 V;
R
GS
= 50
Ω;
V
GS
= 10 V;
T
j(init)
= 25 °C; unclamped
Min
-
Typ
79
Max
-
Unit
nC
Table 1.
Symbol
Q
GD
Dynamic characteristics
Avalanche ruggedness
E
DS(AL)S
non-repetitive
drain-source
avalanche energy
-
-
770
mJ
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
mb
Pinning information
Symbol Description
G
S
S
D
S
S
S
D
gate
source
source
drain
[1]
source
source
source
mounting base;
connected to drain
4
123 567
mb
D
Simplified outline
Graphic symbol
G
mbb076
S
SOT427 (D2PAK)
[1]
It is not possible to connect to pin 4 of the SOT427 package.
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK6C2R1-55C
D2PAK
Description
Version
plastic single-ended surface-mounted package (D2PAK); 7 leads SOT427
(one lead cropped)
Type number
BUK6C2R1-55C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 18 January 2012
2 of 13
NXP Semiconductors
BUK6C2R1-55C
N-channel TrenchMOS intermediate level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
GS
I
D
Limiting values
Parameter
drain-source voltage
gate-source voltage
drain current
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
Pulsed
DC
T
mb
= 25 °C; V
GS
= 10 V; see
Figure 1
T
amb
= 100 °C; V
GS
= 10 V;
see
Figure 1
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
T
mb
= 25 °C
pulsed; t
p
≤
10 µs; T
mb
= 25 °C
I
D
= 120 A; V
sup
≤
55 V; R
GS
= 50
Ω;
V
GS
= 10 V; T
j(init)
= 25 °C; unclamped
T
mb
= 25 °C; pulsed; t
p
≤
10 µs;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
[1]
[2]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Min
-
-20
-16
-
-
-
-
-55
-55
-
-
-
Max
55
20
16
228
162
914
300
175
175
228
914
770
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
Source-drain diode
Avalanche ruggedness
[1]
[2]
Accumulated pulse duration not to exceed 5mins.
-16V accumulated duration not to exceed 168 hrs.
250
I
D
(A)
200
003aaf964
120
P
der
(%)
80
03na19
150
100
40
50
0
0
50
100
150
200
T
mb
(
°
C)
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Continuous drain current as a function of
mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
BUK6C2R1-55C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 18 January 2012
3 of 13
NXP Semiconductors
BUK6C2R1-55C
N-channel TrenchMOS intermediate level FET
10
4
I
D
(A)
10
3
Limit R
DSon
= V
DS
/ I
D
t
p
=10
μ
s
10
2
100
μ
s
003aaf965
10
1 ms
DC
1
10 ms
100 ms
10
-1
10
-1
1
10
10
2
V
DS
(V)
10
3
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance from junction to mounting base
Conditions
see
Figure 4
Min
-
Typ
-
Max
0.5
Unit
K/W
1
Z
th(j-mb)
(K/W)
10
-1
δ
= 0.5
0.2
0.1
0.05
0.02
10
-2
single shot
t
p
T
P
003aaf930
δ
=
t
p
T
t
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK6C2R1-55C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 18 January 2012
4 of 13
NXP Semiconductors
BUK6C2R1-55C
N-channel TrenchMOS intermediate level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
V
GSth
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
see
Figure 9;
see
Figure 10
I
D
= 2.5 mA; V
DS
= V
GS
; T
j
= 175 °C;
see
Figure 10
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
see
Figure 10
I
DSS
I
GSS
R
DSon
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= 55 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 55 V; V
GS
= 0 V; T
j
= 175 °C
V
GS
= 20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; I
D
= 90 A; T
j
= 25 °C;
see
Figure 11
V
GS
= 5 V; I
D
= 90 A; T
j
= 25 °C;
see
Figure 11
V
GS
= 4.5 V; I
D
= 90 A; T
j
= 25 °C;
see
Figure 11
V
GS
10 V; I
D
= 90 A; T
j
= 175 °C;
see
Figure 11;
see
Figure 12
Dynamic characteristics
Q
G(tot)
total gate charge
I
D
= 180 A; V
DS
= 44 V; V
GS
= 10 V;
see
Figure 13;
see
Figure 14
I
D
= 180 A; V
DS
= 44 V; V
GS
= 5 V;
see
Figure 13;
see
Figure 14
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
reverse recovery time
recovered charge
I
S
= 80 A; V
GS
= 0 V; T
j
= 25 °C;
see
Figure 16
I
S
= 50 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
V
DS
= 30 V; T
j
= 25 °C
V
DS
= 30 V; R
L
= 0.3
Ω;
V
GS
= 10 V;
R
G(ext)
= 10
Ω
I
D
= 180 A; V
DS
= 44 V; V
GS
= 10 V;
see
Figure 13;
see
Figure 14
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
253
140
40
79
12000
1075
730
43
206
412
190
0.8
56
115
-
-
-
-
16000
1290
1000
-
-
-
-
1.2
-
-
nC
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
Min
55
50
1.8
0.8
-
-
-
-
-
-
-
-
-
Typ
-
-
2.3
-
-
0.04
-
2
2
1.9
2.4
2.6
-
Max
-
-
2.8
-
3.3
1
500
100
100
2.3
3.1
3.7
5.7
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
mΩ
Static characteristics
Source-drain diode
BUK6C2R1-55C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 18 January 2012
5 of 13
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