DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16732D
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The
µ
PD16732D is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is
based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors
by output of 64 values
γ
-corrected by an internal D/A converter and 5-by-2 external power modules. Because the
output dynamic range is as large as V
SS2
+ 0.1 V to V
DD2
– 0.1 V, level inversion operation of the LCD’s common
electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line
inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit
whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a
maximum clock frequency of 65 MHz when driving at 3.0 V, 45 MHz when driving at 2.3 V, this driver is applicable to
XGA-standard TFT-LCD panels and SXGA TFT-LCD panels.
FEATURES
•
CMOS level input (2.3 to 3.6 V)
•
384 outputs
•
Input of 6 bits (gray-scale data) by 6 dots
•
Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
•
Logic power supply voltage (V
DD1
): 2.3 to 3.6 V
•
Driver power supply voltage (V
DD2
): 8.0 to 9.0 V
•
High-speed data transfer: f
CLK
= 65 MHz (internal data transfer speed when operating at V
DD1
= 3.0 V)
•
Output dynamic range: V
SS2
+ 0.1 V to V
DD2
– 0.1 V
•
Apply for dot-line inversion, n-line inversion and column line inversion
•
Output voltage polarity inversion function (POL)
•
Display data inversion function (capable of controlling by each input port) (POL21,POL22)
•
Current consumption control function (LPC, Bcont)
•
Succession of
µ
PD16732A driver
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
µ
PD16732DN-xxx
Remark
The TCP’s external shape is customized. To order the required shape, so please contact one of our
sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15022EJ1V0DS00 (1st edition)
Date Published June 2002 NS CP (K)
Printed in Japan
The mark
5
shows major revised points.
©
2001,2002
µ
PD16732D
1. BLOCK DIAGRAM
STHR
R,/L
CLK
STB
C
1
C
2
STHL
V
DD1
V
SS1
C
63
C
64
64-bit bidirectional shift register
D
00 -
D
05
D
10 -
D
15
D
20 -
D
25
D
30 -
D
35
D
40 -
D
45
D
50 -
D
55
POL21,POL22
Data register
POL
Latch
V
DD2
Level shifter
V
SS2
V
0 -
V
9
D/A converter
LPC
Bcont
Voltage follower output
S
1
S
2
S
3
S
384
Remark
/xxx indicates active low signal.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S
1
S
2
S
383
S
384
V
0
V
4
V
5
V
9
Multi-
plexer
5
6-bit D/A converter
5
POL
2
Data Sheet S15022EJ1V0DS
µ
PD16732D
3. PIN CONFIGURATION (Top of copper foil surface, face-up)
µ
PD16732DN-xxx: TCP (TAB package)
STHL
D
55
D
54
D
53
D
52
D
51
D
50
D
45
D
44
D
43
D
42
D
41
D
40
D
35
D
34
D
33
D
32
D
31
D
30
V
DD1
R,/L
V
9
V
8
V
7
V
6
V
5
V
DD2
V
SS2
Bcont
V
4
V
3
V
2
V
1
V
0
V
SS1
LPC
CLK
STB
POL
POL21
POL22
D
25
D
24
D
23
D
22
D
21
D
20
D
15
D
14
D
13
D
12
D
11
D
10
D
05
D
04
D
03
D
02
D
01
D
00
STHR
S
384
S
383
S
382
S
381
Copper foil
surface
S
4
S
3
S
2
S
1
Remark
This figure does not specify the TCP package.
Data Sheet S15022EJ1V0DS
3
µ
PD16732D
4. PIN FUNCTIONS
(1/2)
Pin Symbol
S
1
to S
384
D
00
to D
05
D
10
to D
15
D
20
to D
25
D
30
to D
35
D
40
to D
45
D
50
to D
55
R,/L
Shift direction control
Input
The shift direction control pin of the shift register. The shift directions of the shift
registers are as follows.
R,/L = H (right shift): STHR (input), S
1
→
S
384
, STHL (output)
R,/L = L (left shift) : STHL (input), S
384
→
S
1
, STHR (output)
STHR
Right shift start pulse
I/O
These refer to the start pulse I/O pins when the IC is connected in cascade.
Loading of display data starts when a high level is read at the rising edge of CLK.
A high level should be input as the pulse of one cycle of the clock signal.
STHL
Left shift start pulse
I/O
If the start pulse input is more than 2CLKs, the first 1CLK of the high-level input is
valid.
R,/L = H (right shift): STHR input, STHL output
R,/L = L (left shift): STHL input, STHR output
CLK
Shift clock
Input
This pin refers to the shift clock input of the shift register. The display data is
loaded into the data register at the rising edge. At the rising edge of the 64th after
the start pulse input, the start pulse output reaches the high level, thus becoming
the start pulse of the next-level driver. When the 66 clock pulses are input after
input of the start pulse, input of display data is halted automatically. The contents
of the shift register are cleared at the STB’s rising edge.
STB
Latch
Input
The contents of the data register are transferred to the latch circuit at the rising
edge. In addition, at the falling edge, the gray scale voltage is supplied to the
driver. It is necessary to ensure input of one pulse per horizontal period.
POL
Polarity input
Input
POL = L: The S
2n–1
output uses V
0
to V
4
as the reference supply. The S
2n
output
uses V
5
to V
9
as the reference supply.
POL = H: The S
2n–1
output uses V
5
to V
9
as the reference supply. The S
2n
output
uses V
0
to V
4
as the reference supply.
S
2n-1
indicates the odd output: and S
2n
indicates the even output. Input of the POL
signal is allowed the setup time (t
POL
-
STB
) with respect to STB’s rising edge.
POL21,
POL22
Data inversion
Input
Select of inversion or no inversion for input data.
POL21: D
00
-D
05
, D
10
-D
15
, D
20
-D
25
Data inversion or no inversion of Port1
POL22: D
30
-D
35
, D
40
-D
45
, D
50
-D
55
Data inversion or no inversion of Port2
POL21,POL22 = H: Data are inverted in the IC.
POL21,POL22 = L: Data are not inverted in the IC.
LPC
Low power control
Input
The current consumption is lowered by controlling the constant current source of
the output amplifier. In low power mode (LPC = L), the V
DD2
of static current
consumption can be reduced to two thirds of the normal current consumption. This
pin is pulled up to the V
DD1
power supply inside the IC.
LPC = H or open: Normal power mode
LPC = L: Low power mode
Bcont
Bias control
Input
This pin can be used to finely control the bias current inside the output amplifier. In
cases when fine-control is necessary, connect this pin to the stabilized ground
potential (V
SS2
) via an external resistor of 10 to 100 kΩ (per IC).
When this fine-control function is not required, leave this pin open.
Refer to
9. CURRENT CONSUMPTION REDUCTION FUNCTION
Driver
Display data
Pin Name
I/O
Output
Input
Description
The D/A converted 64-gray-scale analog voltage is output.
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by
6 dots (2 pixels).
D
X0
: LSB, D
X5
: MSB
5
4
Data Sheet S15022EJ1V0DS
µ
PD16732D
(2/2)
Pin Symbol
V
0
to V
9
Pin Name
I/O
−
Description
Input the
γ
-corrected power supplies from outside by using operational amplifier.
Make sure to maintain the following relationships. During the gray scale voltage
output, be sure to keep the gray scale level power supply at a constant level.
V
DD2
−
0.1 V
≥
V
0
> V
1
> V
2
> V
3
> V
4
≥
0.5 V
DD2
0.5 V
DD2
≥
V
5
> V
6
> V
7
> V
8
> V
9
≥
V
SS2
+ 0.1 V
V
DD1
V
DD2
V
SS1
V
SS2
Logic power supply
Driver power supply
Logic ground
Driver ground
−
−
−
−
2.3 to 3.6 V
8.0 to 9.0 V
Grounding
Grounding
γ
-corrected power
supplies
Cautions 1. The power start sequence must be V
DD1
, logic input, and V
DD2
& V
0
to V
9
in that order.
Reverse this sequence to shut down (Simultaneous power application to V
DD2
and V
0
to V
9
is
possible.).
2. To stabilize the supply voltage, please be sure to insert a 0.1
µ
F bypass capacitor between
V
DD1
-V
SS1
and V
DD2
-V
SS2
. Furthermore, for increased precision of the D/A converter, insertion
of a bypass capacitor of about 0.01
µ
F is also recommended between the
γ
-corrected power
supply terminals (V
0
, V
1
, V
2
,....., V
9
) and V
SS2
.
Data Sheet S15022EJ1V0DS
5
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