电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

HD74ALVCH16821T

产品描述ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, TSSOP-56
产品类别逻辑    逻辑   
文件大小51KB,共12页
制造商Renesas(瑞萨电子)
官网地址https://www.renesas.com/
下载文档 详细参数 全文预览

HD74ALVCH16821T概述

ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, TSSOP-56

HD74ALVCH16821T规格参数

参数名称属性值
厂商名称Renesas(瑞萨电子)
零件包装代码TSSOP
包装说明TSSOP,
针数56
Reach Compliance Codecompliant
系列ALVC/VCX/A
JESD-30 代码R-PDSO-G56
长度14 mm
逻辑集成电路类型BUS DRIVER
位数10
功能数量2
端口数量2
端子数量56
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd)5.8 ns
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2.3 V
标称供电电压 (Vsup)2.5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式GULL WING
端子节距0.5 mm
端子位置DUAL
宽度6.1 mm

文档预览

下载PDF文档
HD74ALVCH16821
3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs
ADE-205-171B (Z)
3rd. Edition
December 1999
Description
The HD74ALVCH16821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are
edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides
true data at the Q outputs. A buffered output enable (OE) input can be used to place the ten outputs in
either a normal logic state (high or low levels) or a high impedance state. In the high impedance state, the
outputs neither load nor drive the bus lines significantly. The high impedance state and increased drive
provide the capability to drive bus line without need for interface or pullup components. The output enable
(OE) input does not affect the internal operations of the flip flops. Old data can be retained or new data can
be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided to hold
unused or floating data inputs at a valid logic level.
Features
V
CC
= 2.3 V to 3.6 V
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25°C)
High output current
±24
mA (@V
CC
= 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 2854  955  583  25  1616  48  16  44  21  42 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved