HD74ALVCH16270
12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs
ADE-205-137 (Z)
Preliminary 1st. Edition
May 1996
Description
The HD74ALVCH16270 is used in applications where data must be transferred from a narrow high
speed bus to a wide lower frequency bus. The device provides synchronous data exchange between the
two ports. Data is stored in the internal registers on the low to high transition of the clock (CLK) input
when the appropriate
CLKEN
inputs are low. The select (SEL) line selects 1B or 2B data for the A
outputs. For data transfer in the A to B direction, a two stage pipeline is provided in the A to 1B path,
with a single storage register in the A to 2B path. Proper control of the
CLKENA
inputs allows two
sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is
controlled by the active low output enables (OEA,
OEB).
The control terminals are registered to
synchronize the bus direction changes with CLK. Active bus hold circuitry is provided to hold unused
or floating data inputs at a valid logic level.
Features
•
V
CC
= 2.3 V to 3.6 V
•
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
•
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25°C)
•
High output current ±24 mA (@V
CC
= 3.0 V)
•
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
HD74ALVCH16270
Function Table
Inputs
CLK
↑
↑
↑
↑
OEA
H
H
L
L
OEB
H
L
H
L
Outputs
A
Z
Z
Active
Active
1B, 2B
Z
Active
Z
Active
Output enable
Inputs
CLKENA1
L
L
L
L
H
H
H
CLKENA2
H
H
L
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
X
A
L
H
L
H
L
H
X
Outputs
1B
L
*2
2B
2B
0
2B
0
L
H
*1
*1
*1
*1
*1
H
*2
L
*2
H
*2
1B
0
1B
0
1B
0
L
H
2B
0
*1
A-to-B storage (OEB = L)
Inputs
CLKEN1B
H
X
L
L
X
X
CLKEN2B
X
H
X
X
L
L
CLK
X
X
↑
↑
↑
↑
SEL
H
L
H
H
L
L
1B
X
X
L
H
X
X
2B
X
X
X
X
L
H
Output A
A
0
A
0
L
H
L
H
*1
*1
B-to-A storage (OEA = L)
H : High level
L : Low level
X : Immaterial
Z : High impedance
↑
: Low to high transition
Notes: 1. Output level before the indicated steady state input conditions were established.
2. Two CLK edges are needed to propagate data.
HD74ALVCH16270
Pin Arrangement
OEA
1
CLKEN1B
2
2B3 3
GND 4
2B2 5
2B1 6
V
CC
7
A1 8
A2 9
A3 10
GND 11
A4 12
A5 13
A6 14
A7 15
A8 16
A9 17
GND 18
A10 19
A11 20
A12 21
V
CC
22
1B1 23
1B2 24
GND 25
1B3 26
CLKEN2B
27
SEL
28
56
OEB
55
CLKENA2
54 2B4
53 GND
52 2B5
51 2B6
50 V
CC
49 2B7
48 2B8
47 2B9
46 GND
45 2B10
44 2B11
43 2B12
42 1B12
41 1B11
40 1B10
39 GND
38 1B9
37 1B8
36 1B7
35 V
CC
34 1B6
33 1B5
32 GND
31 1B4
30
CLKENA1
29 CLK
(Top view)
HD74ALVCH16270
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
*1, 2
Symbol
V
CC
V
I
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to V
CC
+0.5
Output voltage
*1, 2
Input clamp current
Output clamp current
Continuous output current
V
O
I
IK
I
OK
I
O
–0.5 to V
CC
+0.5
–50
±50
±50
±100
Maximum power dissipation
at Ta = 55°C (in still air)
*3
Storage temperature
Notes:
P
T
Tstg
1
–65 to 150
W
°C
TSSOP
V
mA
mA
mA
V
I
< 0
V
O
< 0 or V
O
> V
CC
V
O
= 0 to V
CC
Unit
V
V
Except I/O ports
I/O ports
Conditions
Stresses beyond those listed under “absolute maximum ratings” may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute maximum rated conditions for extended
periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output
clamp current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of
150°C and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Supply voltage
Input voltage
Output voltage
High level output current
Symbol
V
CC
V
I
V
O
I
OH
Min
2.3
0
0
—
—
—
Low level output current
I
OL
—
—
—
Input transition rise or fall rate
Operating temperature
∆t
/
∆v
Ta
0
–40
Max
3.6
V
CC
V
CC
–12
–12
–24
12
12
24
10
85
ns / V
°C
mA
Unit
V
V
V
mA
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V
Conditions
Note: Unused control inputs must be held high or low to prevent them from floating.
HD74ALVCH16270
Logic Diagram
CLK
CLKEN1B
CLKEN2B
CLKENA1
CLKENA2
OEB
SEL
OEA
29
2
27
30
55
C1
56
28
1
1D
1D
C1
G1
1
1
CE
C1
1D
CE
C1
1D
CE
C1
1D
CE
C1
1D
CE
C1
1D
1 of 12 Channels
23
1B1
A1
8
6
2B1
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