HDMP-1022 Transmitter
HDMP-1024 Receiver
Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os
Technical Data
Description
The HDMP-1022 transmitter and the HDMP-1024 re-
ceiver are used to build a high-speed data link for point-
to-point communication. The monolithic silicon bipolar
transmitter chip and receiver chip are each provided in
a standard Thermally Enhanced PQFP package.
From the user’s viewpoint, these products can be
thought of as providing a “virtual ribbon cable” inter-
face for the transmission of data. Parallel data (a frame)
loaded into the Tx (transmitter) chip is delivered to the
Rx (receiver) chip over a serial channel, which can be
either a coaxial copper cable or optical link, and is re-
constructed into its original parallel form.
The chip set hides from the user all the complexity of
encoding, multiplexing, clock extraction, demultiplex-
ing and decoding. Unlike other links, the phase-locked-
loop clock extraction circuit also transparently provides
for frame synchronization–the user is not troubled with
the periodic insertion of frame synchronization words.
In addition, the DC balance of the line code is auto-
matically maintained by the chip set. Thus, the user can
transmit arbitrary data without restriction. The Rx chip
also includes a state-machine controller (SMC) that pro-
vides a startup handshake protocol for the duplex link
configuration.
The serial data rate of the Tx/Rx link is selectable in four
ranges (see tables on page 5), and extends from 120
Mbits/s up to 1.25 Gbits/s. This translates into an en-
coded serial rate of 150-1500 MBaud. The parallel data
interface is 16 or 20 bit TTL, pin selectable. A flag bit is
available and can be used as an extra 17th or 21st bit
under the user’s control. The flag bit can also be used
as an even or odd frame indicator for dual-frame trans-
mission. If not used, the link performs expanded error
detection.
The serial link is synchronous, and both frame synchro-
nization and bit synchronization are maintained. When
data is not available to send, the link maintains synchro-
nization by transmitting fill frames. Two (training) fill
frames are reserved for handshaking during link startup.
User control space is also supported. If Control Available
(CAV) is asserted at the Tx chip, the least significant 14
or 18 bits of the data are sent and the Rx Control Avail-
able (CAV) line will indicate the data as a Control Word.
Features
• Virtual Ribbon Cable Replacement
• On-Chip Encode / Decode
• On-Chip State Machine for Fully Automatic Link
Management
• On-Chip Tx/Rx PLL Provides Frame Synchronization
• High Speed Serial Rate:
- 150-1500 MBaud (User Selectable)
• Standard TTL Interface:
- 16, 17, 20, or 21 Bits Wide
• Implemented in a Thermally Enhanced PQFP Package
Applications
• Backplane Serialization/ Bus Extender
• Video, Image Acquisition
• Point to Point Data Links
• Implement SCI-FI Standard
• Implement Serial HIPPI Specification
Table of Contents
Topic ................................................................................................................................................................................................................Page
Typical Applications ............................................................................................................................................................................................3
Setting the Operating Rate ...............................................................................................................................................................................4
Transmitter Block Diagram ...............................................................................................................................................................................6
Receiver Block Diagram .....................................................................................................................................................................................8
Transmitter Timing Characteristics ............................................................................................................................................................. 10
Receiver Timing Characteristics ................................................................................................................................................................... 11
DC Electrical Specifications............................................................................................................................................................................ 12
AC Electrical Specifications ............................................................................................................................................................................ 12
Typical Lock-Up Times ..................................................................................................................................................................................... 12
Latency .................................................................................................................................................................................................................. 12
Absolute Maximum Ratings .......................................................................................................................................................................... 13
Thermal Characteristics................................................................................................................................................................................... 13
Pin-Out Diagrams .............................................................................................................................................................................................. 14
Package Mark Description ............................................................................................................................................................................. 15
I/O Type Definitions .......................................................................................................................................................................................... 15
Transmitter Pin Definitions ............................................................................................................................................................................ 16
Receiver Pin Definitions .................................................................................................................................................................................. 20
Mechanical Dimensions and Package Information .............................................................................................................................. 23
Recommended Handling Precautions....................................................................................................................................................... 23
Appendix I: Additional Internal Architecture Information ............................................................................................................... 24
Line Code Description ..................................................................................................................................................................................... 24
Data Frame Codes ............................................................................................................................................................................................. 24
Control Frame Codes ....................................................................................................................................................................................... 25
Fill Frame Codes ................................................................................................................................................................................................. 26
Tx Operation Principles ................................................................................................................................................................................... 27
Tx Encoding ......................................................................................................................................................................................................... 27
Tx Phase Locked Loop ..................................................................................................................................................................................... 28
Rx Operation Principles ................................................................................................................................................................................... 29
Rx Encoding......................................................................................................................................................................................................... 29
HDMP-1024 (Rx) Phase Locked Loop ......................................................................................................................................................... 30
HDMP-1024 (Rx) Decoding ............................................................................................................................................................................ 30
HDMP-1024 (Rx) Link Control State Machine Operation Principle .................................................................................................. 31
The State Machine Handshake Protocol ................................................................................................................................................... 31
Appendix II: Link Configuration Examples ........................................................................................................................................... 33
Duplex/Simplex Configurations................................................................................................................................................................... 33
Full Duplex ........................................................................................................................................................................................................... 33
Simplex Method I: Simplex with Low Speed Return Path ................................................................................................................. 34
Simplex Method II: Simplex with Periodic Sync Pulse......................................................................................................................... 34
Simplex Method III: Simplex with External Reference Oscillator .................................................................................................... 35
Data Interface for Single/Double Frame Mode ...................................................................................................................................... 35
Single Frame Mode (MDFSEL=0) ................................................................................................................................................................. 36
Double Frame Mode (MDFSEL=1) ............................................................................................................................................................... 36
Supply Bypassing and Integrator Capacitor ............................................................................................................................................ 37
Integrating Capacitor ....................................................................................................................................................................................... 38
Power Supply Bypassing and Grounding ................................................................................................................................................. 38
Electrical Connections ..................................................................................................................................................................................... 39
I-TTL and O-TTL .................................................................................................................................................................................................. 39
High Speed Interface: I-H50 & O-BLL ........................................................................................................................................................ 39
Mode Options ..................................................................................................................................................................................................... 40
2
Typical Applications
The HDMP-1022/1024 chipset was designed for ease
of use and flexibility. This allows the customer to tailor
the use of this product, through the configuration of
the link, based on his specific system requirements
and application needs. Typical applications range from
backplane serialization and bus extension to digital
video transmission.
Low latency bus extension of a 16 or 20 bit wide data
bus may be achieved using the standard duplex con-
figuration (see Figure 1d). In full duplex, the HDMP-
1022/1024 chipset handles all of the issues of link
startup, maintenance, and simple error detection.
If the bus width is 32 or 40 bits wide, the HDMP-
1022/1024 chipset is capable of sending this data
frame as two separate frame segments with the use
of an external mux and demux as shown in Figure 1b.
In this mode, called Double Frame Mode, the FLAG bit
is used by the transmitter and receiver to indicate the
first or second frame segment (Figure 19). The HDMP-
1022/1024 chipset in Double Frame Mode may also be
configured in full duplex to achieve a 32/40 bit wide
bus extension.
For digital video transmission, simplex links are more
common. The HDMP-1022/1024 chipset can transmit 16
to 20 bits of parallel data in standard or broadcast sim-
plex mode (Figs. 1a, 1e). Additionally, 32 to 40 bit wide
data can be transmitted over a single line (in Double
Frame Mode) or two parallel lines, as in Figure 1c.
For timing diagrams for the standard configurations,
see the Appendix section entitled Link Configuration
Examples.
The HDMP-1022/1024 chipset can support serial trans-
mission rates from 150 MBd to 1.5 GBd for each of these
configurations. The chipset requires the user to input
the link data rate by asserting DIV1 and DIV0 accord-
ingly. To determine the DIV1/DIV0 setting necessary for
each application, refer to the section: Setting the Oper-
ating Data Rate Range below.
CLK
Tx
Rx
CLK
A) 16/20 BIT SIMPLEX TRANSMISSION
MUX
CLK
Tx
Rx
CLK
DEMUX
B) 32/40 BIT SIMPLEX TRANSMISSION
CLK
Tx
Rx
CLK
CLK
Tx
Rx
CLK
C) 32/40 BIT SIMPLEX TRANSMISSION
WITH HIGH CLOCK RATES
CLK
Tx
Rx
CLK
CLK
Rx
Tx
CLK
D) 16/20 BIT DUPLEX TRANSMISSION
CLK
Tx
Rx
CLK
Rx
CLK
Rx
CLK
E) SIMPLEX BROADCAST TRANSMISSION
Figure 1. Various Configurations Using the HDMP-1022/1024.
3
Setting the Operating Data Rate Range
The HDMP-1022/1024 chipset can operate from 150
MBaud to 1500 MBaud. It is divided into four operating
data ranges with each range selected by setting DIV1
and DIV0 as shown in the tables on the following page.
The purpose of the following example is to help in
understanding and using these tables. This specific ex-
ample uses the table in Figure 3 entitled “Typical 20 Bit
Mode Data Rates.”
It is desired to transmit a 20 bit parallel word operating
at 55 MHz (55 MWord/sec). Both the Tx and Rx must be
set to a range that covers this word rate. According to
the table entitled “Typical Operating Rates for 20 Bit
Mode” on the next page, a setting of DIV1/DIV0 = 0/0 al-
lows a parallel input word rate of 35.8 to 62.5 MHz . This
setting easily accommodates the required 55 MHz word
rate. The user serial data rate can be calculated as:
20 bit 55 Mw
Serial Data Rate = (––––––)(––––––)
word
sec
= 1100 MBits/sec
The baud rate includes an additional 4 bits that G-LINK
transmits for link control and error detection. The serial
baud rate is calculated as:
24 bit 55 Mw
Serial Data Rate = (––––––)(––––––)
word
sec
= 1320 MBaud
The 55 MHz example is one in which the parallel word
rate provides only one possible DIV1/DIV0 setting.
Some applications may have a parallel word rate that
seems to fit two ranges. As an example, a 37 MHz (37
MWord/s) parallel data rate falls within two ranges
(DIV0/DIV1 = 0/0 and DIV1/DIV0 = 0/1) in 20 Bit Mode.
Per the table, a setting of DIV1/DIV0 = 0/1 gives an up-
per rate of 38.6 MHz , while a setting of DIV1/DIV0 = 0/0
gives a lower rate of 35.8 MHz. These transition data
rates are stated in the tables as typical values and may
vary between individual parts. Each transmitter/receiver
has continuous band coverage across its entire 150 to
1500 MBaud range and has overlap between ranges. In
this example, each transmitter/receiver will permit a 37
MHz parallel data rate, but it is suggested that DIV0 be a
jumper that can be set either to logic ‘1’ (open) or logic
‘0’ (ground). This allows the design to accommodate
both ranges for maximum flexibility. This technique is
recommended whenever operating near the maximum
and minimum of two word rate ranges. The above in-
formation also applies to the HDMP-1022/1024 chipset
when operating in 16 bit mode.
4
HDMP-1022 (Tx), HDMP-1024 (Rx)
Typical Operating Rates for 16 Bit Mode
[1]
Tc = 0°C to +85°C, V
CC
= 4.5 V to 5.5 V
DIV1
0
0
1
1
DIV0
0
1
0
1
Parallel Word Rate Range Serial Data Rate Range
(Mword/sec)
(Mbit/sec)
43
22.7
11.0
7.5 (min)
75 (max)
46.3
25.2
12.2
687
363
177
120 (min)
1200 (max)
741
403
196
Serial Baud Rate Range
(MBaud)
860
454
220
150 (min)
1500 (max)
926
504
245
Notes:
1. All values are typical unless otherwise noted by (min) or (max). (min) indicates the minimum guaranteed value although typical values are
lower. (max) indicates the maximum guaranteed value although typical values are higher.
2. All values in this table are expected for a BER less than 10
-14
.
FRAME RATE (Mwords/sec)
5
0/0
DIV 1 / DIV 0
0/1
1/0
1/1
175
100
100
225
500
1000
1500
2000
2500
350
450
BAUD RATE = 20 x FRAME RATE
25
700
900
50
75
1800
100
125
SERIAL DATA RATE (Mbaud)
Figure 2. Typical 16 Bit Mode Data Rates Showing Continuous Range of Operation with Band Overlap.
HDMP-1022 fig 2
DIV1
DIV0
Parallel Word Rate
(Mword/sec)
Range
35.8
18.9
9.2
6.3 (min)
25
700
Serial Data Rate
(Mbit/sec)
Range
716
378
184
125 (min)
50
Serial Baud Rate
(MBaud)
Range
860
454
220
150 (min)
100
1800
0
0
1
1
4
0/0
DIV 1 / DIV 0
0/1
1/0
1/1
100
100
0
1
0
1
62.5 (max)
38.6
21.0
10.2
1250 (max)
772
420
204
75
1500 (max)
926
504
245
FRAME RATE (Mwords/sec)
350
175
225
500
450
900
BAUD RATE = 24 x FRAME RATE
1000
1500
2000
2500
SERIAL DATA RATE (Mbaud)
Figure 3. Typical 20 Bit Mode Data Rates Showing Continuous Range of Operation with Band Overlap.
5
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