IDT74AUC16374
1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
1.8V CMOS 16-BIT EDGE-
TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
FEATURES:
DESCRIPTION:
IDT74AUC16374
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• 1.8V Optimized
• 0.8V to 2.7V Operating Range
• Inputs/outputs tolerant up to 3.6V
• Output drivers: ±9mA @ 2.3V
• Supports hot insertion
• Available in TSSOP, TVSOP, and VFBGA packages
APPLICATIONS:
• high performance, low voltage communications systems
• high performance, low voltage computing systems
This 16-bit edge-triggered D-type flip-flop is built using advanced CMOS
technology. The AUC16374 is particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and working registers. It can be
used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the
clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data
(D) inputs.
OE
can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the
outputs neither load nor drive the bus lines significantly. The high-impedance
state and the increased drive provide the capability to drive bus lines without
need for interface or pullup components.
OE
does not affect the internal operation
of the flip-flop. Old data can be retained or new data can be entered while the
outputs are in the high-impedance state.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the outputs, preventing damaging current backflow
through the device when it is powered down.
To ensure the high-impedance state during power up or power down,
OE
should be tied to V
DD
through a pull-up resistor; the minimum value of the resistor
is determined by the current-sinking capability of the driver.
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
CLK
2
OE
2
CLK
C
1
1
Q
1
1
D
1
1
D
2
D
1
C
1
2
Q
1
1
D
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2003 Integrated Device Technology, Inc.
JANUARY 2003
DSC-6179/5
IDT74AUC16374
1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
PINOUT CONFIGURATION
6
1CLK
1D2
1D4
1D6
1D8
2D1
2D3
2D5
2D7
2CLK
5
NC
1D1
1D3
1D5
1D7
2D2
2D4
2D6
2D8
NC
4
NC
GND
V
DD
GND
GND
V
DD
GND
NC
3
NC
GND
V
DD
GND
GND
V
DD
GND
NC
2
NC
1Q1
1Q3
1Q5
1Q7
2Q2
2Q4
2Q6
2Q8
NC
1
1OE
1Q2
1Q4
1Q6
1Q8
2Q1
2Q3
2Q5
2Q7
2OE
A
B
C
D
E
VFBGA
F
G
H
J
K
NOTE:
NC = No Internal Connection
56 BALL VFBGA PACKAGE LAYOUT
A
6
5
4
3
2
1
B
C
D
E
F
G
H
J
K
TOP VIEW
2
IDT74AUC16374
1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Description
Terminal Voltage with Respect to GND
(all input and V
DD
terminals)
V
TERM
Terminal Voltage with Respect to GND
(any I/O or Output terminals in high-
impedance or power-off state)
T
STG
I
OUT
I
IK
I
OK
I
DD
I
SS
Storage Temperature
Continuous DC Output Current
Continuous Clamp Current,
V
I
< 0, or V
I
> V
DD
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
DD
or GND
–50
±100
mA
mA
–65 to +150
±20
±50
°C
mA
mA
–0.5 to +3.6
V
Max
–0.5 to +3.6
Unit
V
1
OE
1
Q
1
1
Q
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
CLK
1
D
1
1
D
2
GND
1
Q
3
1
Q
4
GND
1
D
3
1
D
4
V
DD
1
Q
5
1
Q
6
V
DD
1
D
5
1
D
6
GND
1
Q
7
1
Q
8
2
Q
1
2
Q
2
GND
1
D
7
1
D
8
2
D
1
2
D
2
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
GND
2
Q
3
2
Q
4
GND
2
D
3
2
D
4
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz, V
DD
= 2.5V)
Symbol
C
IN
(1)
C
OUT
(2)
C
I
(3)
Parameter
Input Capacitance
Output Capacitance
Input Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
3
5
3
Max.
Unit
pF
pF
pF
V
DD
2
Q
5
2
Q
6
V
DD
2
D
5
2
D
6
GND
2
Q
7
2
Q
8
2
OE
GND
2
D
7
2
D
8
2
CLK
NOTES:
1. Applies to Control Inputs.
2. Applies to Data Outputs.
3. Applies to Data Inputs.
FUNCTION TABLE
(EACH FLIP-FLOP)
(1)
Inputs
Output
xDx
H
L
X
X
xQx
H
L
Q
(2)
Z
xOE
L
L
L
H
xCLK
↑
↑
H or L
X
TSSOP/ TVSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
xDx
xCLK
xQx
xOE
Data Inputs
Clock Inputs
3-State Outputs
3-State Output Enable Inputs (Active LOW)
Description
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
↑
= LOW-to-HIGH Transition
2. Level of Q before the indicated steady-state conditions were established.
3
IDT74AUC16374
1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
RECOMMENDED OPERATING CHARACTERISTICS
(1)
Symbol
V
DD
Parameter
Supply Voltage
V
DD
= 0.8V
V
DD
= 1.1V to 1.3V
V
IH
Input HIGH Voltage Level
V
DD
= 1.4V to 1.6V
V
DD
= 1.65V to 1.95V
V
DD
= 2.3V to 2.7V
V
DD
= 0.8V
V
DD
= 1.1V to 1.3V
V
IL
Input LOW Voltage Level
V
DD
= 1.4V to 1.6V
V
DD
= 1.65V to 1.95V
V
DD
= 2.3V to 2.7V
V
I
V
O
Input Voltage
Output Voltage
Active State
3-State
V
DD
= 0.8V
V
DD
= 1.1V
I
OH
HIGH Level Output Current
V
DD
= 1.4V
V
DD
= 1.65V
V
DD
= 2.3V
V
DD
= 0.8V
V
DD
= 1.1V
I
OL
LOW Level Output Current
V
DD
= 1.4V
V
DD
= 1.65V
V
DD
= 2.3V
∆t/∆v
T
A
Input Transition Rise or Fall Time
Operating Free-Air Temperature
Test Conditions
Min.
0.8
V
DD
0.65 x V
DD
0.65 x V
DD
0.65 x V
DD
1.7
—
—
—
—
—
0
0
0
—
—
—
—
—
—
—
—
—
—
—
–40
Max.
2.7
—
—
—
—
—
0
0.35 x V
DD
0.35 x V
DD
0.35 x V
DD
0.7
2.7
V
DD
2.7
–0.7
–3
–5
–8
–9
0.7
3
5
8
9
20
+85
ns/V
°C
mA
mA
V
V
V
V
Unit
V
NOTE:
1. All unused inputs of the device must be held at V
DD
or GND to ensure proper operation.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
(1)
Following Conditions Apply Unless Otherwise Specified:
Operating Conditions: T
A
= –40°C to +85°C
Symbol
I
IH
I
IL
I
OFF
I
OZH
I
OZL
I
DDL
I
DDH
I
DDZ
NOTE:
1. All unused inputs of the device must be held at V
DD
or GND to ensure proper operation.
Parameter
Input HIGH or LOW Current
All Inputs
Input/Output Power Off Leakage
High Impedance Output Current
(3-State Output Pins)
Quiescent Power Supply Current
Test Conditions
V
DD
= 2.7V, V
I
= V
DD
or GND
V
DD =
0V, V
IN or
V
O
≤
2.7V
V
DD
= 2.7V
V
DD
= 0.8V to 2.7V
V
IN
= GND or V
DD
V
O
= V
DD
V
O
= GND
Min.
—
—
—
—
—
Typ.
—
—
—
—
—
Max.
±5
±10
±10
±10
20
Unit
µA
µA
µA
µA
4
IDT74AUC16374
1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
Test Conditions
(1)
V
DD
= 0.8V - 2.7V
I
OH
= –100µA
V
DD
= 0.8V
I
OH
= –0.7mA
I
OH
= –3mA
V
DD
= 1.1V
(2)
(3)
I
OH
= –5mA
V
DD
= 1.4V
V
DD
= 1.65V
(4)
I
OH
= –8mA
(5)
V
DD
= 2.3V
I
OH
= –9mA
V
DD
= 0.8V - 2.7V
I
OH
= 100µA
V
DD
= 0.8V
I
OL
= 0.7mA
(2)
I
OL
= 3mA
V
DD
= 1.1V
I
OL
= 5mA
V
DD
= 1.4V
(3)
(4)
V
DD
= 1.65V
I
OL
= 8mA
I
OH
= 9mA
V
DD
= 2.3V
(5)
Min.
V
DD
- 0.1
—
0.8
1
1.2
1.8
—
—
—
—
—
—
Typ.
—
0.55
—
—
—
—
—
0.25
—
—
—
—
Max.
—
—
—
—
—
—
0.2
—
0.3
0.4
0.45
0.6
Unit
V
V
OL
Output LOW Voltage
V
NOTES:
1. V
IL
and V
IH
must be within
2. Demonstrates operation for
3. Demonstrates operation for
4. Demonstrates operation for
5. Demonstrates operation for
the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS table for the appropriate V
DD
range. T
A
= -40°C to +85°C.
nominal V
DD
= 1.2V.
nominal V
DD
= 1.5V.
nominal V
DD
= 1.8V.
nominal V
DD
= 2.5V.
OPERATING CHARACTERISTICS, T
A
= 25°C
(1)
Symbol
C
PD
(each
output)
C
PD(Z)
Parameter
Power Dissipation Capacitance
(2)
Outputs Enabled,
1 Output Switching
Power Dissipation Capacitance
Outputs Disabled,
1 Clock and 1 Data Switching
Power Dissipation Capacitance
(3)
Outputs Disabled,
Clock Only Switching
Test Conditions
1 f
DATA
= 5MHz
1 f
CLK
= 10MHz
1 f
OUT
= 5MHz
OE
= GND, C
L
= 0pF
1 f
DATA
= 5MHz
1 f
CLK
= 10MHz
f
OUT
= not switching
OE
= V
DD
, C
L
= 0pF
1 f
DATA
= 0MHz
1 f
CLK
= 10MHz
f
OUT
= not switching
OE
= V
DD
, C
L
= 0pF
V
DD
= 0.8V V
DD
= 1.2V V
DD
= 1.5V V
DD
= 1.8V V
DD
= 2.5V Unit
24
24
24.1
26.2
31.2
pF
7.5
7.5
8
9.4
13.2
pF
C
PD
(each
clock)
13.8
13.8
14
14.7
17.5
pF
NOTES:
1. Total device C
PD
for multiple (x) outputs switching and (n) clocks inputs switching = {x * C
PD
(each output)} + {n C
PD
(each clock)}.
2. C
PD
(each output). This is the C
PD
for each data bit where each input and output circuit is operating at 5MHz. The clock frequency is 10MHz and the numbers shown are
minus the I
DD
component.
3. C
PD
(each clock); this is the C
PD
for each clock circuit, operating at 10MHz.
5
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