IDT74LVCH32373A
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH32373A
3.3V CMOS 32-BIT
TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O, BUS-HOLD
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
µ
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in 96-ball LFBGA package
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
• Balanced Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
The LVCH32373A 32-bit transparent D-type latch is built using advanced
dual metal CMOS technology. This high-speed, low-power latch is ideal
for temporary storage of data. The device can be used for implementing
memory address latches, I/O ports, and bus drivers. The Output Enable
and Latch Enable controls are organized to operate each device as four 8-
bit latches, two 16-bit latches, or one 32-bit latch. Flow-through organization
of signal pins simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
All pins of the LVCH32373A can be driven from either 3.3V or 5V devices.
This feature allows the use of this device as a translator in a mixed 3.3V/
5V supply system.
The LVCH32373A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH32373A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1
OE
A3
3
OE
J3
1
LE
A4
3
LE
J4
D
1
A5
D
A2
3
D
1
J5
D
C
J2
C
1
Q
1
3
Q
1
TO SEVEN OTHER CHANNELS
T3
TO SEVEN OTHER CHANNELS
2
OE
H3
4
OE
2
LE
H4
4
LE
T4
2
D
1
E5
D
E2
4
D
1
2
Q
1
N5
D
C
N2
C
4
Q
1
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TO SEVEN OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
1
©2000 Integrated Device Technology, Inc.
JANUARY 2000
DSC-4765/1
IDT74LVCH32373A
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
6
1
D
2
1
D
4
1
D
6
1
D
8
2
D
2
2
D
4
2
D
6
2
D
7
3
D
2
3
D
4
3
D
6
3
D
8
4
D
2
4
D
4
4
D
6
4
D
7
5
1
D
1
1
D
3
1
D
5
1
D
7
2
D
1
2
D
3
2
D
5
2
D
8
3
D
1
3
D
3
3
D
5
3
D
7
4
D
1
4
D
3
4
D
5
4
D
8
4
1
LE
GND
GND
1
Q
3
V
CC
V
CC
1
Q
5
GND
GND
1
Q
7
GND
GND
2
Q
1
V
CC
V
CC
2
Q
3
GND
GND
2
Q
5
2
LE
3
LE
GND
GND
3
Q
3
V
CC
V
CC
3
Q
5
GND
GND
3
Q
7
GND
GND
4
Q
1
V
CC
V
CC
4
Q
3
GND
4
LE
3 1
OE
2
OE
3
OE
GND
4
Q
5
4
OE
2
1
Q
1
2
Q
8
3
Q
1
4
Q
8
1
1
Q
2
A
1
Q
4
B
1
Q
6
C
1
Q
8
D
2
Q
2
E
2
Q
4
F
2
Q
6
G
2
Q
7
H
3
Q
2
J
3
Q
4
K
3
Q
6
L
3
Q
8
M
4
Q
2
N
4
Q
4
P
4
Q
6
R
4
Q
7
T
LFBGA
TOPVIEW
96 BALL LFBGA PACKAGE ATTRIBUTES
1.5 mm Max.
1.4 mm Nom.
1.3 mm Min.
0.8mm
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
TOP VIEW
A
1
2
3
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
5.5mm
4
5
6
13.5mm
2
IDT74LVCH32373A
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
V
TERM
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through each
V
CC
or GND
–0.5 to +6.5
–65 to +150
–50 to +50
–50
±100
Unit
V
°C
mA
mA
mA
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
6.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
NOTE:
1. As applicable to the device type.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Names
xDx
xLE
xOE
xQx
Data Inputs
(1)
Latch Enable Inputs (Active HIGH)
Output Enable Inputs (Active LOW)
3-State Outputs
Description
FUNCTION TABLE
(EACH 8-BIT SECTION)
(1)
Inputs
xOE
L
L
H
L
xLE
H
H
X
L
xDx
H
L
X
X
Outputs
xQx
H
L
Z
Q
(2)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
2. Output level of Q before the indicated steady-state conditions were established.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
—
—
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
±500
Unit
µA
µA
µA
3
IDT74LVCH32373A
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
—
—
—
—
—
—
—
–0.7
100
—
—
—
±50
–1.2
—
10
10
500
µA
V
mV
µA
V
CC
= 3.6V
V
O
= 0 to 5.5V
—
—
±10
µA
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
Test Conditions
Min.
1.7
2
—
—
—
Typ.
(1)
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
µA
V
Unit
V
Quiescent Power Supply Current
Variation
3.6
≤
V
IN
≤
5.5V
(2)
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
µA
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
2.2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
4
IDT74LVCH32373A
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, V
CC
= 3.3V ± 0.3V, T
A
= 25°C
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance per Latch Outputs enabled
Power Dissipation Capacitance per Latch Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
78
12
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.7V
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK
(o)
Parameter
Propagation Delay
xDx to xQx
Propagation Delay
xLE to xQx
Output Enable Time
xOE to xQx
Output Disable Time
xOE to xQx
Set-up Time HIGH or LOW, xDx to xLE
Hold Time HIGH or LOW, xDx after xLE
xLE Pulse Width HIGH
Output Skew
(2)
1.7
1.2
3.3
—
—
—
—
—
1.7
1.2
3.3
—
—
—
—
500
ns
ns
ns
ps
1.5
6.3
2.5
5.9
ns
1.5
5.7
1.3
4.7
ns
2
5.3
2.1
4.6
ns
Min.
1.5
Max.
4.9
V
CC
= 3.3V ± 0.3V
Min.
1.6
Max.
4.2
Unit
ns
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
5
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