gate version of Fairchild Semiconductor’s advanced
PowerTrench process. It has been optimized for power
management applications with a wide range of gate
drive voltage (1.8V – 8V).
Features
•
–13.5 A, –20 V. R
DS(ON)
= 8.5 mΩ @ V
GS
= –4.5 V
R
DS(ON)
= 10.5 mΩ @ V
GS
= –2.5 V
R
DS(ON)
= 14 mΩ @ V
GS
= –1.8 V
•
Fast switching speed
•
High performance trench technology for extremely
low R
DS(ON)
•
High current and power handling capability
Applications
•
Power management
•
Load switch
•
Battery protection
D
D
D
D
SO-8
D
D
D
D
5
6
7
4
3
2
1
Pin 1
SO-8
G
S
G
S
S
S
S
S
T
A
=25 C unless otherwise noted
o
8
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Drain-Source Voltage
Gate-Source Voltage
Drain Current
– Continuous
– Pulsed
Parameter
Ratings
–
20
±8
(Note 1a)
Units
V
V
A
W
–
13.5
–
50
2.5
1.5
1.2
-55 to +175
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
T
J
, T
STG
Operating and Storage Junction Temperature Range
°C
Thermal Characteristics
R
θJA
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1c)
(Note 1)
50
125
25
°C/W
°C/W
°C/W
Package Marking and Ordering Information
Device Marking
4467
Device
Si4467DY
Reel Size
13’’
Tape width
12mm
Quantity
2500 units
2001
Fairchild Semiconductor International
Si4467DY Rev A
Si4467DY
Electrical Characteristics
Symbol
BV
DSS
∆BV
DSS
∆T
J
I
DSS
I
GSSF
I
GSSR
T
A
= 25°C unless otherwise noted
Parameter
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
(Note 2)
Test Conditions
V
GS
= 0 V, I
D
= –250
µA
I
D
= –250
µA,
Referenced to 25°C
V
DS
= –16 V,
V
GS
= 8 V,
V
GS
= –8 V,
V
GS
= 0 V
V
DS
= 0 V
V
DS
= 0 V
Min
–20
Typ
Max Units
V
Off Characteristics
–12
–1
100
–100
mV/°C
µA
nA
nA
On Characteristics
V
GS(th)
∆V
GS(th)
∆T
J
R
DS(on)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
V
DS
= V
GS
, I
D
= –250
µA
I
D
= –250
µA,
Referenced to 25°C
V
GS
= –4.5 V,
I
D
= –13.5 A
I
D
= –12 A
V
GS
= –2.5 V,
I
D
= –10.5 A
V
GS
= –1.8 V,
V
GS
=–4.5 V, I
D
=–13.5A, T
J
=125°C
V
GS
= –4.5 V,
V
DS
= –5 V,
V
DS
= –5 V
I
D
= –13.5 A
–0.4
–0.6
3
6.7
8.0
9.8
9.0
–1.5
V
mV/°C
8.5
10.5
14
13
mΩ
I
D(on)
g
FS
On–State Drain Current
Forward Transconductance
–50
70
A
S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(Note 2)
V
DS
= –10 V,
f = 1.0 MHz
V
GS
= 0 V,
8237
1497
750
pF
pF
pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
V
DD
= –10V,
V
GS
= –4.5 V,
I
D
= –1 A,
R
GEN
= 6
Ω
20
24
300
140
36
38
480
224
120
ns
ns
ns
ns
nC
nC
nC
V
DS
= –10 V,
V
GS
= –4.5 V
I
D
= –13.5 A,
86
20
11
Drain–Source Diode Characteristics and Maximum Ratings
I
S
V
SD
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
V
GS
= 0 V, I
S
= –2.1 A
Voltage
–2.1
(Note 2)
A
V
–0.6
–1.2
Notes:
1.
R
θJA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
FPGA/CPLD
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