INTEGRATED CIRCUITS
PTN3310/PTN3311
High-speed serial logic translators
Product data
Supersedes data of 2002 Oct 24
2004 Feb 24
Philips
Semiconductors
Philips Semiconductors
Product data
High-speed serial logic translators
PTN3310/PTN3311
FEATURES
•
Meets LVDS EIA-644 and PECL standards
•
2 pin-for-pin replacement input/output choices:
–
LVDS in, PECL out (PTN3310)
–
PECL in, LVDS out (PTN3311)
PIN CONFIGURATIONS
GND1
V
INP
V
INN
GND2
1
2
8
7
V
CC1
V
OUTP
V
OUTN
V
CC2
PTN3310
3
4
6
5
•
Single +3.3 V supply voltage operation
•
Available in 8-pin SO or TSSOP package
•
Maximum throughput data rate of 800 Mbps typical
APPLICATIONS
–
ATM
–
SONET/SDH
–
Switches
–
Routers
–
Add-drop multiplexers
GND1
V
INP
1
2
8
7
V
CC1
V
OUTP
V
OUTN
V
CC2
•
High-speed networking and telecom applications
PTN3311
V
INN
GND2
3
4
6
5
8-pin SO package
ST00014
GENERAL DESCRIPTION
The High-Speed Serial Logic Translator provides a point solution
that addresses the various interface logic requirements of Optical
Transceiver Modules. The product offers a compact translation
between LVDS and PECL high speed serial data lines. This provides
the end users a simple way to mix or match Optical Transceiver ICs
from various vendors to maximize desired performance and reduces
the need to redesign interfaces to accommodate new Optical
Transceiver ICs.
The High-Speed Serial Logic Translator comes in two translation
choices to allow mixing LVDS and PECL input/outputs. The product
is offered in a small, convenient, 8-pin package.
Figure 1 shows the High-Speed Serial Logic Translator Device in a
typical high speed optical module application. Figure 2 shows the
circuit block diagrams.
PIN DESCRIPTIONS
8-pin SO and TSSOP package
Pin #
1, 4
2, 3
5, 8
6, 7
Symbol
GND1, GND2
V
INP
, V
INN
V
CC1
, V
CC2
V
OUTN
, V
OUTP
Name and function
Ground
Differential inputs
Supply voltage
Differential outputs
ORDERING INFORMATION
Type number
n mber
PTN3310D
PTN3311D
PTN3310DP
PTN3311DP
Package
Name
SO8
SO8
TSSOP8
TSSOP8
Description
Plastic small-outline package; 8 leads; body width 3.9 mm
Plastic small-outline package; 8 leads; body width 3.9 mm
plastic thin shrink small outline package; 8 leads; body width 3 mm
plastic thin shrink small outline package; 8 leads; body width 3 mm
Version
SOT96-1
SOT96-1
SOT505-1
SOT505-1
2004 Feb 24
2
Philips Semiconductors
Product data
High-speed serial logic translators
PTN3310/PTN3311
Optical
RCVR
Optical
Laser
Driver
Translator
MAC
(ASIC)
Translator
Serial
Backplane
Device
To/From
Serial
Backplane
Optical Interface IC’s
1 x 9 Optical Module
Figure 1. High-Speed Serial Logic Translators in Optical Module Application
ST00040
LVDS IN
PECL OUT
PTN3310
PECL IN
LVDS OUT
PTN3311
ST00009
Figure 2. High-Speed Serial Logic Translator Block Diagrams
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
t
SC
T
j
T
stg
ESD
HBM
ESD
MM
Parameter
Supply voltage
LVDS receiver input voltage
LVDS driver output voltage
LVDS output short circuit duration
Maximum junction temperature
Storage temperature range
Electrostatic discharge (Human Body Model, 1.5 kΩ, 100 pF)
Electrostatic discharge (Machine Model, 0 kΩ, 200 pF)
Limits
–0.3 to +4.0
–0.3 to +5.5
–0.3 to +5.5
continuous
+150
–65 to +150
>2
>200
°C
°C
kV
V
Unit
V
V
V
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
T
amb
V
CCN
Parameter
Supply voltage
Operating ambient temperature range in free air
Power supply noise voltage
Min
3.0
–40
–
Max
3.6
+85
100
Unit
V
°C
mV
PP
2004 Feb 24
3
Philips Semiconductors
Product data
High-speed serial logic translators
PTN3310/PTN3311
DC ELECTRICAL CHARACTERISTICS
Symbol
General
V
CC
I
CC
I
EE
V
IH
V
IL
I
I
V
ID
I
IN
Supply voltage
Power supply current
Power supply current
Input HIGH voltage
1
Input LOW
voltage
1
V
IN
= V
CC
or GND
Input current
Minimum differential input signal amplitude
Input current
2
V
IN
= 0 V
V
IN
= V
CC
PECL outputs (PTN3310)
V
OH
V
OL
C
L
V
OD
∆
V
OD
V
OS
∆
V
OS
I
OS
C
L
Output HIGH voltage
1
Output LOW voltage
1
Output load capacitance
Output differential voltage
Steady-state difference in output differential
voltage between complementary output states
Offset voltage
Steady-state difference in offset voltage between
complementary output states
Output short-circuit current
Output load capacitance
outputs mutually shorted
output shorted to GND
2.275
1.490
–
250
–
1.125
–
–
–
–
2.345
1.595
5
350
–
1.250
–
–
–
5
2.420
1.680
–
450
50
1.375
50
12
24
–
V
V
pF
mV
mV
V
mV
mA
mA
pF
PTN3311
PTN3310
3.0
–
–
2.135
1.490
–
100
–
–
3.3
12
13
–
–
–
–
–
–
3.6
20
20
2.420
1.825
±10
–
20
20
V
mA
mA
V
V
µA
mV
mA
mA
Parameter
Conditions
Min
Typ
Max
Unit
PECL inputs (PTN3311)
LVDS inputs (PTN3310)
LVDS outputs (PTN3311); R
L
= 100
Ω
NOTES:
1. These values are for V
CC
= 3.3 V; PECL level specifications are referenced to V
CC
and will track 1:1 with variation of V
CC
.
2. Power supply either on or off.
2004 Feb 24
4
Philips Semiconductors
Product data
High-speed serial logic translators
PTN3310/PTN3311
AC ELECTRICAL CHARACTERISTICS
Symbol
General
f
MAX
t
S
SKEW
t
PLH
/t
PHL
Maximum throughput data rate
Clock output skew, part-to-part
Clock output pulse skew
Propagation delay input (differential) to output
Propagation delay input (single-ended) to output
Output rise and fall times at 20% and 80%
intersects
Transition time LOW to HIGH
Transition time HIGH to LOW
Peak-to-peak switching offset voltage
R
L
= 100
Ω;
C
L
= 5 pF
R
L
= 100
Ω;
C
L
= 5 pF
Measured between two
matched 49.9
Ω
load resistors;
5 pF load capacitance
655
–
–
–
–
800
100
50
1
1
–
–
–
3
3
Mbps
ps
ps
ns
ns
Parameter
Conditions
Min
Typ
Max
Unit
PECL outputs (PTN3310)
t
r
/t
f
–
200
300
ps
LVDS outputs (PTN3311); R
L
= 100
Ω;
C
L
= 5 pF
t
TLH
t
THL
V
OSS
–
–
–
500
500
–
650
650
150
ps
ps
mV
LVDS REFERENCE MEASUREMENT CONFIGURATION
Voutp
PTN331x
1
2
3
4
5
6
7
8
C
LVDS
R
load
C
probe
Vos
R
load
Voutn
C
probe
V
OD
= V
OUTP
– V
OUTN
R
load
= 50
Ω
C
LVDS
= 5 pF
ST00041
Figure 3.
The above diagram shows the test set-up used when evaluating
LVDS outputs. According to the TIA-EIA-644 Standard, the
maximum lumped capacitance test load should be 5 pF. However,
by using probes or cables to observe the signal, additional
capacitance is added, which has an effect on the rise and fall times.
C
probe
represents any capacitance caused by the use of probes or
cables. Assuming balanced loading and balanced output drivers, the
total effective capacitance seen by the part is:
C
Eff
= C
LVDS
+
1
/
2
To correctly account for the effects of C
probe
, the following formula
should be used:
5 pF
Dt
+
C
Dt
Eff
measured,
Where
∆t
is the 20%–80% rise/fall time.
To avoid the use of additional calculation of the measured results, a
different approach could be taken; however, the value of C
probe
has
to be known in advance. In that case, the value of C
LVDS
can be
chosen such that the sum of the capacitances equals 5 pF, i.e.:
C
LVDS
+
1
/
2
C
probe
= 5 pF
C
probe
2004 Feb 24
5
FPGA/CPLD
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