Cortina Systems
®
LXT9785 and
LXT9785E Advanced 8-Port 10/
100 Mbps PHY Transceivers
Datasheet
The Cortina Systems
®
LXT9785 and LXT9785E are 8-port Fast Ethernet PHY Transceivers supporting
IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices provide Serial/Source
Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent
Interface (RMII) for switching and other independent port applications. The LXT9785 and LXT9785E are
identical except for the IP telephony features included in the LXT9785E transceiver. The LXT9785E is an
enhanced version of the LXT9785 that detects Data Terminal Equipment (DTE) requiring power from the
switch over a CAT5 cable. The system uses the information collected by the LXT9785E to apply power if
the DTE at the far end requires power over the cable, such as an IP telephone.
Each network port can provide a twisted-pair (TP) or Low-Voltage Positive Emitter Coupled Logic
(LVPECL) interface. The twisted-pair interface supports 10 Mbps and 100 Mbps (10BASE-T and
100BASE-TX) Ethernet over twisted-pair. The LVPECL interface supports 100 Mbps (100BASE-FX)
Ethernet over fiber-optic media.
The LXT9785/LXT9785E provides three discrete LED driver outputs for each port. The devices support
both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a single 2.5 V
power supply.
Applications
Enterprise switches
IP telephony switches
Storage Area Networks
Multi-port Network Interface Cards (NICs)
Product Features
Eight IEEE 802.3-compliant 10BASE-T or
100BASE-TX ports with integrated filters.
100BASE-FX fiber-optic capability on all ports.
2.5 V operation.
Low power consumption; 250 mW per port
typical.
Multiple RMII or SMII/SS-SMII ports for
independent PHY port operation.
Auto MDI/MDIX crossover capability.
Proprietary Optimal Signal Processing™
architecture improves SNR by 3 dB over ideal
analog filters.
Optimized for dual-high stacked RJ-45
applications.
MDIO sectionalization into 2x4 or 1x8
configurations.
Supports both auto-negotiation systems and
legacy systems without auto-negotiation
capability.
Robust baseline wander correction.
Configurable through the MDIO port or external
control pins.
JTAG boundary scan.
208-pin PQFP: LXT9785HC, LXT9785EHC,
LXT9785HE.
241-ball BGA: LXT9785BC, LXT9785EBC.
196-ball BGA: LXT9785MBC (includes DTE
detection similar to the LXT9785E)
DTE detection for remote powering applications
(LXT9785E and LXT9785MBC only).
Extended temperature operation of -40
o
C to
+85
o
C (LXT9785E only).
LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Contents
Contents
1.0
Introduction..................................................................................................................................18
1.1
1.2
2.0
3.0
What You Will Find in This Document ................................................................................18
Related Documents ............................................................................................................18
Block Diagram .............................................................................................................................19
Pin/Ball Assignments and Signal Descriptions ........................................................................20
3.1
PQFP Pin Assignments ......................................................................................................20
3.1.1 PQFP Pin Assignments – RMII Configuration .......................................................20
3.1.2 PQFP Pin Assignments – SMII Configuration........................................................26
3.1.3 PQFP Pin Assignments – SS-SMII Configuration..................................................31
PQFP Signal Descriptions ..................................................................................................36
3.2.1 Signal Name Conventions .....................................................................................36
3.2.2 PQFP Signal Descriptions – RMII, SMII, and SS-SMII Configurations..................36
BGA23 Ball Assignments....................................................................................................51
3.3.1 RMII BGA23 Ball List .............................................................................................52
3.3.2 SMII BGA23 Ball List .............................................................................................61
3.3.3 SS-SMII BGA23 Ball List .......................................................................................70
BGA23 Signal Descriptions ................................................................................................79
3.4.1 Signal Name Conventions .....................................................................................79
3.4.2 Signal Descriptions – RMII, SMII, and SS-SMII Configurations.............................80
BGA15 Ball Assignments....................................................................................................97
3.5.1 BGA15 Ball List......................................................................................................98
BGA15 Signal Descriptions ..............................................................................................106
3.6.1 Signal Name Conventions ...................................................................................106
3.6.2 Signal Descriptions – SMII and SS-SMII Configurations .....................................106
Introduction .......................................................................................................................113
4.1.1 OSP™ Architecture .............................................................................................113
4.1.2 Comprehensive Functionality ..............................................................................114
4.1.2.1 Sectionalization....................................................................................114
Interface Descriptions .......................................................................................................114
4.2.1 10/100 Network Interface.....................................................................................114
4.2.1.1 Twisted-Pair Interface ..........................................................................115
4.2.1.2 MDI Crossover (MDIX).........................................................................116
4.2.1.3 Fiber Interface......................................................................................116
Media Independent Interface (MII) Interfaces ...................................................................116
4.3.1 Global MII Mode Select .......................................................................................117
4.3.2 Internal Loopback ................................................................................................117
4.3.3 RMII Data Interface..............................................................................................118
4.3.4 Serial Media Independent Interface (SMII) and Source Synchronous- Serial Media
Independent Interface (SS-SMII) .........................................................................118
4.3.4.1 SMII Interface.......................................................................................118
4.3.4.2 Source Synchronous-Serial Media Independent Interface ..................118
4.3.5 Configuration Management Interface ..................................................................118
4.3.6 MII Isolate ............................................................................................................118
4.3.7 MDIO Management Interface ..............................................................................119
4.3.8 MII Sectionalization..............................................................................................120
3.2
3.3
3.4
3.5
3.6
4.0
Functional Description..............................................................................................................113
4.1
4.2
4.3
Cortina Systems
®
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Page 2
LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Contents
4.4
4.5
4.6
4.7
4.8
4.9
4.3.9 MII Interrupts........................................................................................................120
4.3.10 Global Hardware Control Interface ......................................................................121
4.3.11 FIFO Initial Fill Values..........................................................................................121
Operating Requirements...................................................................................................122
4.4.1 Power Requirements ...........................................................................................122
4.4.2 Clock/SYNC Requirements..................................................................................122
4.4.2.1 Reference Clock ..................................................................................122
4.4.2.2 TxCLK Signal (SS-SMII only)...............................................................122
4.4.2.3 TxSYNC Signal (SMII/SS-SMII) ...........................................................122
4.4.2.4 RxSYNC Signal (SS-SMII only) ...........................................................122
4.4.2.5 RxCLK Signal (SS-SMII Only) .............................................................123
Initialization .......................................................................................................................123
4.5.1 MDIO Control Mode .............................................................................................123
4.5.2 Hardware Control Mode.......................................................................................123
4.5.3 Power-Down Mode ..............................................................................................124
4.5.3.1 Global (Hardware) Power Down ..........................................................125
4.5.3.2 Port (Software) Power Down ...............................................................125
4.5.4 Reset ...................................................................................................................125
4.5.5 Hardware Configuration Settings .........................................................................126
Link Establishment............................................................................................................126
4.6.1 Auto-Negotiation ..................................................................................................126
4.6.1.1 Base Page Exchange ..........................................................................126
4.6.1.2 Manual Next Page Exchange ..............................................................126
4.6.1.3 Controlling Auto-Negotiation ................................................................127
4.6.1.4 Link Criteria..........................................................................................127
4.6.1.5 Parallel Detection.................................................................................127
4.6.1.6 Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced
Speed Mode.........................................................................................128
Serial MII Operation ..........................................................................................................128
4.7.1 SMII Reference Clock ..........................................................................................132
4.7.2 TxSYNC Pulse (SMII/SS-SMII)............................................................................132
4.7.3 Transmit Data Stream..........................................................................................132
4.7.3.1 Transmit Enable...................................................................................132
4.7.3.2 Transmit Error ......................................................................................132
4.7.4 Receive Data Stream...........................................................................................133
4.7.4.1 Carrier Sense.......................................................................................133
4.7.4.2 Receive Data Valid ..............................................................................133
4.7.4.3 Receive Error .......................................................................................133
4.7.4.4 Receive Status Encoding.....................................................................133
4.7.5 Collision ...............................................................................................................133
4.7.6 Source Synchronous-Serial Media Independent Interface ..................................134
RMII Operation .................................................................................................................137
4.8.1 RMII Reference Clock..........................................................................................137
4.8.2 Transmit Enable...................................................................................................138
4.8.3 Carrier Sense & Data Valid..................................................................................138
4.8.4 Receive Error .......................................................................................................138
4.8.5 Out-of-Band Signaling .........................................................................................138
100 Mbps Operation .........................................................................................................141
4.9.1 100BASE-X Network Operations .........................................................................141
4.9.2 100BASE-X Protocol Sublayer Operations..........................................................141
4.9.2.1 PCS Sublayer ......................................................................................141
Cortina Systems
®
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Page 3
LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Contents
4.10
4.11
4.12
4.13
4.14
PMA Sublayer ......................................................................................................142
4.9.3.1 Link ......................................................................................................143
4.9.3.2 Link Failure Override............................................................................144
4.9.3.3 Carrier Sense/Data Valid (RMII) ..........................................................144
4.9.3.4 Carrier Sense (SMII) ............................................................................144
4.9.3.5 Receive Data Valid (SMII)....................................................................144
4.9.3.6 Twisted-Pair PMD Sublayer.................................................................144
4.9.3.7 Fiber PMD Sublayer.............................................................................145
10 Mbps Operation ...........................................................................................................146
4.10.1 Preamble Handling ..............................................................................................146
4.10.2 Dribble Bits ..........................................................................................................146
4.10.3 Link Test ..............................................................................................................146
4.10.3.1 Link Failure ..........................................................................................147
4.10.4 Jabber ..................................................................................................................147
DTE Discovery Process ....................................................................................................147
4.11.1 Definitions ............................................................................................................148
4.11.2 Interaction between Processor, MAC, and PHY ..................................................148
4.11.3 Management Interface and Control .....................................................................149
4.11.4 DTE Discovery Process Flow ..............................................................................150
4.11.5 DTE Discovery Behavior......................................................................................151
Monitoring Operations ......................................................................................................153
4.12.1 Monitoring Auto-Negotiation ................................................................................153
4.12.2 Per-Port LED Driver Functions ............................................................................153
4.12.3 Out-of-Band Signaling .........................................................................................154
4.12.4 Boundary Scan Interface .....................................................................................155
4.12.5 State Machine ......................................................................................................155
4.12.6 Instruction Register ..............................................................................................155
4.12.7 Boundary Scan Register ......................................................................................156
Cable Diagnostics Overview .............................................................................................156
4.13.1 Features...............................................................................................................156
4.13.2 Operation .............................................................................................................157
4.13.2.1 Short and Long Cable Testing Requirements......................................157
4.13.2.2 Precision ..............................................................................................157
4.13.3 Implementation Considerations ...........................................................................157
4.13.4 Basic Implementation ..........................................................................................158
Link Hold-Off Overview.....................................................................................................159
4.14.1 Features...............................................................................................................159
4.14.2 Operation .............................................................................................................159
Design Recommendations................................................................................................161
General Design Guidelines ...............................................................................................161
5.2.1 Power Supply Filtering .........................................................................................161
5.2.2 Power and Ground Plane Layout Considerations................................................162
5.2.2.1 Chassis Ground ...................................................................................162
5.2.3 MII Terminations ..................................................................................................162
5.2.4 Twisted-Pair Interface ..........................................................................................162
5.2.4.1 Magnetic Requirements .......................................................................163
5.2.5 The Fiber Interface ..............................................................................................163
5.2.6 LED Circuit...........................................................................................................164
Typical Application Circuits ...............................................................................................165
Page 4
4.9.3
5.0
Application Information ............................................................................................................161
5.1
5.2
5.3
Cortina Systems
®
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Contents
6.0
7.0
8.0
9.0
Test Specifications ....................................................................................................................170
Register Definitions...................................................................................................................191
Package Specifications.............................................................................................................212
8.1
Top Label Markings ..........................................................................................................217
Ordering Information.................................................................................................................219
Cortina Systems
®
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Page 5
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