H8/3006, H8/3007
HD6413006, HD6413007
Hardware Manual
ADE-602-145C
Rev. 4.0
1/29/00
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Preface
The H8/3006 and H8/3007 is a series of high-performance microcontrollers that integrate system
supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include RAM, 16-bit timers, 8-bit timers, a programmable
timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI),
an A/D converter, a D/A converter, I/O ports, and a DMA controller (DMAC).
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently in each area, simplifying the connection of different types of memory. Four
MCU operating modes (modes 1 to 4) are provided, offering a choice of data bus width initial
value and address space.
With these features, the H8/3006 and H8/3007 offers easy implementation of compact, high-
performance systems.
This manual describes the H8/3006 and H8/3007 Series hardware. For details of the instruction
set, refer to the H8/300H Series Programming Manual.
List of Items Revised or Added for This Version
Page
3
28
35
41
45
Item
1.1 Overview
Table 1-1 Feature Watchdog timer (WDT)
2.6.1 Instruction Set Overview
Table 2-7 Bit Manipulation Instructions
2.6.5 Notes on Use of Bit Manipulation Instruction
Explanation
Table 2-13 Effective Address Calculation
Description
Specification description
amended
Number of instruction
types amended
Function description
added
Description added
No. 1 in Addressing Mode
and Instruction Format
column amended
Table amended
Description added
Description added
Description added
Figure amended
Bus cycle B amended
57
57
70
77
144
175
Table 3-1 Operating Mode Selection
3.1.1 Operating Mode Selection
4.2.2 Reset Sequence
5.1.1 Features
Figure 6.15 Example of Wait State Insertion Timing
Figure 6.42 Example of Idle Cycle Operation (2)
(ICIS0 = 1)
(b) Idle cycle inserted
7.4.2 I/O Mode
Table 7.6 Register Functions in I/O Mode
205
Description added
Description added
Description added
Description added
Description added
Description added
Note added
Description amended
Description amended
Reference changed
Description added
Description amended
207
208
210
211
226
248
249
253
7.4.3 Idle Mode
Table 7.7 Register Functions in Idle Mode
7.4.4 Repeat Mode
Table 7.8 Register Functions in Repeat Mode
7.4.8 DMAC Bus Cycle
8.3.2 Register Configuration
Port 6 Data Direction Register (P6DDR)
8.3.2 Register Configuration
Port 6 Data Register (P6DR)
8.5.1 Overview
Figure 8.4 Port 8 Pin Configuration
254
8.5.2 Register Configuration
Port 8 Data Direction Register (P8DDR)
Page
255
258
263
272
273
279 to 346
Item
8.5.2 Register Configuration
Port 8 Data Register (P8DR)
8.6.2 Register Configuration
Port 9 Data Direction Register (P9DDR)
8.7.2 Register Configuration
Port A Data Direction Register (PADDR)
Figure 8.7 Port B Pin Configuration
8.8.2 Register Configuration
Port B Data Direction Register (PBDDR)
Section 9 16-Bit Timers
Description
Description amended
Description amended
Description amended
Description added
Description amended
Register names changed
TCNT
→
16TCNT
TCR
→
16TCR
Register names changed
TCNT
→
8TCNT
TCR
→
8TCR
TCSR
→
8TCSR
8TCSR2 initial value
changed
Description amended
Description added
Note 3 added
Description added to (1)
20.00 MHz value added
20.00 MHz value added
20.00 MHz value added
Restart procedure
amended
Figure amended
Text of 1st note amended
Register names amended
347 to 382
Section 10 8-Bit Timers
351
355
358
411
462
502
503
Table 10.2 8-Bit Timer Register
10.2.4 Timer Control Register (8TCR)
Bits 4 and 3
10.2.5 Timer Control/Status Registers (8TCSR)
Bit 4
Table 12.2 WDT Registers
Figure 13.5 Sample Flowchart for Transmitting Serial
Data
Table 14.5 Bit Rates (bit/s) for Various BRR Settings
(When n = 0)
Table 14.6 BRR Settings for Typical Bit Rates (bits/s)
(When n = 0)
Table 14.7 Maximum Bit Rate for Various Frequencies
(Smart Card Interface Mode)
511
554
556
640, 641
Figure 14.10 Procedure for Stopping and Restarting
the Clock
Figure 18.7 External Clock Output Setting Delay
Timing
18.5.3 Usage Notes
B.1 Addresses
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