based on 8Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM76V16635HGT8 Series
D E S C R IP T IO N
The Hynix HYM76V16635AT8 Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of sixteen 8Mx8bits
CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy
printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB.
The Hynix HYM76V16635AT8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes
memory. The Hyundai HYM76V16635AT8 Series are fully synchronous operation referenced to the positive edge of the clock . All
inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth.
FEATURES
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PC133/PC100MHz support
168pin SDRAM Unbuffered DIMM
Serial Presence Detect with EEPROM
1.25” (31.75mm) Height PCB with double sided com-
ponents
Single 3.3±0.3V power supply
- 1, 2, 4 or 8 or Full page for Sequential Burst
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All device pins are compatible with LVTTL interface
- 1, 2, 4 or 8 for Interleave Burst
Data mask function by DQM
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Programmable CAS Latency ; 2, 3 Clocks
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SDRAM internal banks : four banks
Module bank : two physical bank
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
O R D E R IN G IN F O R M A T IO N
Part No.
HYM76V16635HGT8-K
133MHz
HYM76V16635HGT8-H
4 Banks
4K
Normal
TSOP-II
Gold
Clock
Frequency
Internal
Bank
Ref.
Power
SDRAM
Package
Plating
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.3/Apr.01
P C 1 3 3 S D R A M U n b u ffered DI M
M
HYM76V16635HGT8 Seri
es
P IN D E S C R I T IO N
P
PIN
CK0~CK3
PIN NAME
Clock Inputs
D E S C R IPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
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