with PLL, based on 32Mx8 SDRAM with LVTTL, 4 banks & 8K Refresh
HYM72V64C756K8M Series
DESCRIPTION
The HYM72V64C756K8M H-Series are high speed 3.3-Volt synchronous dynamic RAM Modules composed of eigh-
teen 32Mx8 bit Synchronous DRAMs in 54-pin TSOPII, two 48-pin TSSOP Register Buffers, one 24-pin TSSOP PLL and
8-pin TSSOP 2K bit EEPROM on a 168-pin glass-epoxy printed circuit board. One 0.22µF and one 0.0022µF decoupling
capacitors per each SDRAM are mounted on the module.
The HYM72V64C756K8M H-Series are gold plated socket type Dual In-line Memory Modules suitable for easy inter-
change and addition of 512M bytes memory. All addresses, data and control inputs are latched on the rising edge of the
master clock input. The data paths are internally pipelined to achieve very high bandwidths.
FEATURES
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1.125” (28.56mm) PCB Height
168-Pin Registered DIMM with Double Sided
ECC support
One 0.22µF and one 0.0022µF decoupling
capacitors adopted
Serial Presence Detect with Serial EEPROM
Two Register Buffers & one Inverter used (with
PLL)
Supports Flow-through or Register mode by Pin
No. 147 (REGE)
Meets all the other JEDEC specifications
Single 3.3V±0.3V power supply
All device pins are LVTTL compatible
8192 refresh cycles every 64ms
• Auto precharge/precharge all banks by A
10
flag
• Possible to assert random column address every
clock cycle
• Interleaved auto refresh mode
• Programmable burst lengths and sequences
- 1,2,4,8,full page for Sequential type
- 1,2,4,8 for Interleave type
• Programmable /CAS latency ; 2,3 clocks
• Support clock suspend/power down mode by
CKE0Hynix
• Data mask function by DQM
• Mode register set programming
• Burst termination command
• Self refresh provides minimum power, full internal
ORDERING INFORMATION
Part No.
HYM72V64C756K8M-8
HYM72V64C756K8M-S
Clock
Frequency
125MHz
Internal
Bank
4 Banks
Ref.
Power
SDRAM
Package
TSOP-II
Plating
8K
Normal
Gold
100MHz
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.1/Apr. 2001
PC100 SDRAM Registered DIMM
HYM72V64C756K8M Series
PIN DESCRIPTION
PIN
CK0~CK3
CKE0, CKE1
/S0 ~ /S3
BA0, BA1
A0 ~ A12
/RAS, /CAS, /WE
REGE
DQM0~DQM7
DQ0 ~ DQ63
CB0 ~ CB7
VCC
V
SS
SCL
SDA
SA0~2
WP
NC
PIN NAME
Clock Inputs
Clock Enable
Chip Select
SDRAM Bank Address
Address
Row Address Strobe, Column
Address Strobe, Write Enable
Register Enable
Data Input/Output Mask
Data Input/Output
Check Bit Input/Output
Power Supply (3.3V)
Ground
SPD Clock Input
SPD Data Input/Output
SPD Address Input
Write Protect for SPD
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
嵌入式系统
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