64Mx72 bits
PC100 SDRAM Registered DIMM
with PLL, based on 64Mx4 SDRAM with LVTTL, 4 banks & 8K Refresh
HYM72V64C756B(L)T4 Series
DESCRIPTION
The HYM72V64C756B(L)T4 -Series are high speed 3.3-Volt synchronous dynamic RAM Modules composed of eigh-
teen 64Mx4 bit Synchronous DRAMs in 54-pin TSOPII, two 48-pin SOP Register Buffers, one 24-pin SOP PLL and 8-pin
TSSOP 2K bit EEPROM on a 168-pin glass-epoxy printed circuit board. One 0.22mF and one 0.0022mF decoupling
capacitors per each SDRAM are mounted on the module.
The HYM72V64C756B(L)T4 Series are gold plated socket type Dual In-line Memory Modules suitable for easy inter-
change and addition of 512M bytes memory. All addresses, data and control inputs are latched on the rising edge of the
master clock input. The data paths are internally pipelined to achieve very high bandwidths.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
1.70 (43.18mm) PCB Height
168-Pin Registered DIMM with Double Sided
ECC support
One 0.22µF and one 0.0022µF decoupling
capacitors adopted
Serial Presence Detect with Serial EEPROM
Two Register Buffers & one Inverter used (with
PLL)
Supports Flow-through or Register mode by Pin
No. 147 (REGE)
Meets all the other JEDEC specifications
Single 3.3V±0.3V power supply
All device pins are LVTTL compatible
8192 refresh cycles every 64ms
Auto precharge/precharge all banks by A
10
flag
• Possible to assert random column address every
clock cycle
• Interleaved auto refresh mode
Programmable burst lengths and sequences
- 1,2,4,8,full page for Sequential type
- 1,2,4,8 for Interleave type
• Programmable /CAS latency ; 2,3 clocks
• Support clock suspend/power down mode by
CKE0
• Data mask function by DQM
• Mode register set programming
• Burst termination command
• Self refresh provides minimum power, full internal
refresh control
ORDERING INFORMATION
Part No.
HYM72V64C756BT4-P
HYM72V64C756BT4-S
HYM72V64C756BLT4-P
HYM72V64C756BLT4-S
Clock
Frequency
125MHz
100MHz
125MHz
100MHz
Internal
Bank
Ref.
Power
Normal
SDRAM
Package
Plating
4 Banks
8K
Low Power
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 0.3/Jan. 02
1
PC100 SDRAM Registered DIMM
HYM72V64C756B(L)T4 Series
PIN DESCRIPTION
PIN
CK0~CK3
CKE0
/S0, /S2
BA0, BA1
A0 ~ A12
/RAS, /CAS, /WE
REGE
DQM0~DQM7
DQ0 ~ DQ63
CB0 ~ CB7
VCC
V
SS
SCL
SDA
SA0~2
WP
NC
PIN NAME
Clock Inputs
Clock Enable
Chip Select
SDRAM Bank Address
Address
Row Address Strobe, Column
Address Strobe, Write Enable
Register Enable
Data Input/Output Mask
Data Input/Output
Check Bit Input/Output
Power Supply (3.3V)
Ground
SPD Clock Input
SPD Data Input/Output
SPD Address Input
Write Protect for SPD
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA9, CA11
Auto-precharge flag : A10
/RAS, /CAS and /WE define the operation
Refer function truth table for details
Register Enable pin which permits the DIMM to operateion in Buffered Mode
when REGE input is Low, in Registered Mode when REGE input is High
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Check bits for ECC
Power supply for internal circuits and input buffers
Ground
Serial Presence Detect Clock input
Serial Presence Detect Data input/output
Serial Presence Detect Address Input
Write Protect for Serial Presence Detect on DIMM
No connection
Rev. 0.3/Jan. 02
2
PC100 SDRAM Registered DIMM
HYM72V64C756B(L)T4 Series
PIN ASSIGNMENTS
FRONT SIDE
PIN NO.
1
2
3
4
5
6
7
8
9
10
BACK SIDE
PIN NO.
85
86
87
88
89
90
91
92
93
94
FRONT SIDE
PIN NO.
41
42
43
44
45
46
47
48
49
50
51
52
BACK SIDE
PIN NO.
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
NAME
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NAME
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
NAME
VCC
CK0
VSS
NC
/S2
DQM2
DQM3
NC
VCC
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
NC
NC
NC
VSS
DQ21
DQ22
DQ23
VCC
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
CK2
NC
WP
SDA
SCL
VCC
NAME
*CK1
A12
VSS
CKE0
NC
DQM6
DQM7
NC
VCC
NC
NC
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
NC
NC
REGE
VSS
DQ53
DQ54
DQ55
VCC
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
*CK3
NC
SA0
SA1
SA2
VCC
Architecture Key
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
CB0
CB1
VSS
NC
NC
VCC
/WE
DQM0
DQM1
/S0
NC
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VCC
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
CB4
CB5
VSS
NC
NC
VCC
/CAS
DQM4
DQM5
NC
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Voltage Key
Note : * CK1 ~ CK3 are connected with termination R/C (Rsfer to the block diagram)
Rev. 0.3/Jan. 02
3
PC100 SDRAM Registered DIMM
HYM72V64C756B(L)T4 Series
BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10ohms
2. The padding capacitance of termination R/C for CK1~CK3 is 12pF
Rev. 0.3/Jan. 02
4
PC100 SDRAM Registered DIMM
HYM72V64C756B(L)T4 Series
SERIAL PRESENCE DETECT
BYTE
NUMBER
BYTE0
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
BYTE10
BYTE11
BYTE12
BYTE13
BYTE14
BYTE15
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
BYTE22
BYTE23
BYTE24
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
BYTE31
BYTE32
BYTE33
BYTE34
BYTE35
BYTE36
~61
BYTE62
BYTE63
BYTE64
BYTE65
~71
FUNCTION
DESCRIPTION
# of Bytes Written into Serial Memory at Module
Manufacturer
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
Data Width of This Assembly (Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time @/CAS Latency=3
Access Time from Clock @/CAS Latency=3
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay Back to Back Random Column
Address
Burst Lenth Supported
# of Banks on Each SDRAM Device
SDRAM Device Attributes, /CAS Lataency
SDRAM Device Attributes, /CS Lataency
SDRAM Device Attributes, /WE Lataency
SDRAM Module Attributes
SDRAM Device Attributes, General
SDRAM Cycle Time @/CAS Latency=2
Access Time from Clock @/CAS Latency=2
SDRAM Cycle Time @/CAS Latency=1
Access Time from Clock @/CAS Latency=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active Delay (tRRD)
Minimum /RAS to /CAS Delay (tRCD)
Minimum /RAS Pulse Width (tRAS)
Module Bank Density
Command and Address Signal Input Setup Time
Command and Address Signal Input Hold Time
Data Signal Input Setup Time
Data Signal Input Hold Time
Superset Information (may be used in future)
SPD Revision
Checksum for Byte 0~62
Manufacturer JEDEC ID Code
....Manufacturer JEDEC ID Code
-
Hynix JEDED ID
Unused
Hynix (Korea Area)
HSA (United States Area)
HSE (Europe Area)
HSJ (Japan Area)
HSS(Singapore)
ASIA Area
2ns
1ns
2ns
1ns
-
Intel SPD 1.2B
99h
ADh
FFh
0*h
1*h
2*h
3*h
4*h
5*h
CL=2,3
/CS Latency=0
/WE Latency=0
Registered inputs, with PLL
+/- 10% voltage tolerence, Burst Read
Single Bit Write, Precharge All, Auto
Precharge, Early RAS Precharge
10ns
6ns
-
-
20ns
20ns
20ns
50ns
512MB
2ns
1ns
2ns
1ns
20h
10h
20h
10h
00h
12h
B7h
3, 8
12ns
6ns
-
-
20ns
20ns
20ns
50ns
A0h
60h
00h
00h
14h
14h
14h
32h
80h
20h
10h
20h
10h
10ns
6ns
ECC
7.8125us
/ Self Refresh Supported
x4
x4
tCCD = 1 CLK
1,2,4,8,Full Page
4 Banks
CL=3
06h
01h
01h
16h
0Eh
C0h
60h
00h
00h
14h
14h
14h
32h
FUNCTION
VALUE
-P
128 Bytes
256 Bytes
SDRAM
13
11
1 Bank
72 Bits
-
LVTTL
-S
-P
80h
08h
04h
0Dh
0Bh
01h
48h
00h
01h
-S
NOTE
1
10ns
6ns
A0h
60h
02h
82h
04h
04h
01h
8Fh
04h
A0h
60h
2
04h
BYTE72
Manufacturing Location
9
Rev. 0.3/Jan. 02
5
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