HD66760
104
×
80-dot Graphics LCD Controller/Driver for 256 Colors
ADE-207-335A(Z)
Rev.2.0
September 2001
Description
The HD66760, color-graphics LCD controller and driver LSI, displays 104-by-80-dot graphics for 256 STN
colors. The HD66760's bit-operation functions and a 16-bit high-speed bus interface enable efficient data
transfer and high-speed rewriting of data to the graphics RAM.
The HD66760 has various functions for reducing the power consumption of an LCD system, such as low-
voltage operation of 2.2 V/min., a step-up circuit to generate a maximum of six-times the LCD drive voltage
from the supplied voltage, and voltage-followers to decrease the direct current flow in the LCD drive bleeder-
resistors. Combining these hardware functions with software functions, such as a partial display with low-
duty drive and standby and sleep modes, allows precise power control. The HD66760 is suitable for any mid-
sized or small portable battery-driven product requiring long-term driving capabilities, such as digital cellular
phones supporting a WWW browser, bidirectional pagers, and small PDAs.
Features
104
×
80-dot graphics display LCD controller/driver for 256 STN colors
Display mode change between 256 colors (8 bits per pixel) and four colors (2-bit per pixel)
16/8-bit high-speed bus interface
I2C bus interface
Clock synchronized serial interface
Bit-operation functions for graphics processing:
Write-data mask function in bit units
Swap function of upper and lower bytes
Logical operation in pixel unit and conditional write function
•
Various color-display control functions:
256 of the 4,096 possible colors can be displayed at the same time (grayscale palette incorporated)
Vertical scroll display function in raster-row units
Color window cursor display supported by hardware
•
Low-power operation supports:
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specification.
•
•
•
•
•
•
HD66760
Vcc = 2.2 to 3.6 V (low voltage)
V
LCD
(= V
LPS
– GND) = 5 to 15.5 V (liquid crystal drive voltage)
Three-, four-, five-, or six-times step-up circuit for liquid crystal drive voltage
128-step contrast adjuster and voltage followers to decrease direct current flow in the LCD drive
bleeder-resistors
Power-save functions such as the standby mode and sleep mode
Partial LCD drive of two screens in any position
Programmable drive duty ratios (1/16-1/80) and bias values (1/4-1/10) displayed on LCD
Internal RAM capacity: 8,320 bytes
312-segment
×
80-common liquid crystal display driver
n-raster-row AC liquid-crystal drive (C-pattern waveform drive)
Internal oscillation, hardware reset and software reset
•
•
•
•
•
Shift change of segment and common drivers
2
HD66760
Total Current Consumption Characteristics (Vcc = 3.0 V, TYP Conditions, LCD
Drive Power Current Included)
Total Power Consumption
Normal Display Operation
Character
Display Dot
Size
R-C
Duty Oscillation Frame
Ratio Frequency Frequency
180 kHz
180 kHz
180 kHz
180 kHz
180 kHz
180 kHz
70 Hz
70 Hz
70 Hz
70 Hz
70 Hz
70 Hz
Internal
Logic
(50 µA)
(60 µA)
(100 µA)
(110 µA)
(120 µA)
(130 µA)
LCD
Power
(25 µA)
(25 µA)
(25 µA)
(25 µA)
(25 µA)
(25 µA)
Standby
Mode
Total*
104
×
16 dots 1/16
104
×
24 dots 1/24
104
×
56 dots 1/56
104
×
64 dots 1/64
104
×
72 dots 1/72
104
×
80 dots 1/80
Four-times 0.2 µA
(150 µA)
Four-times
(160 µA)
Five-times
(225 µA)
Five-times
(235 µA)
Six-times
(270 µA)
Six-times
(280 µA)
Note : When a three-, four-, five-, or six-times step-up is used:
the total power consumption = internal logic current + LCD power current x 3 (three-times step-up),
the total power consumption = internal logic current + LCD power current x 4 (four-times step-up),
the total power consumption = internal logic current + LCD power current x 5 (five-times step-up), and
the total power consumption = internal logic current + LCD power current x 6 (six-times step-up)
Type Name
Types
HD66760TB0
HD66760WTxx
HCD66760BP
HCD66760WBP
External Dimensions
Bending TCP
Bending TCP
Au-bumped chip
Au-bumped chip
Interface
Parallel and clock synchronized serial interface
Parallel and I2C interface
Parallel and clock synchronized serial interface
Parallel and I2C interface
3
HD66760
HD66760 Block Diagram
OSC1 OSC2
Vcc
RESET*
TEST
Index register
(IR)
CPG
Control
register (CR)
Timing generator
IM2, IM1,
IM0/ID
7
16
Address counter
(AC)
16
CS*
RS
E/WR*/SCL
RW/RD*/SDA
System interface
16 bits
8 bits
I2C bus
16
Bit operation
Bidirec-
tional
common
shift
register
(80 bits)
COM1-
COM80
Common
driver
16
16
Read data
latch
16
16
14
DB0-DB15
Vci
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
C6+
C6-
VLOUT
VSW1
VSW2
VREG
V1REF
VLREF
VL1REF
Three-, four, five,
and six-times
step-up
Graphics RAM
(GRAM)
8,320 bytes
Latch
circuit
(312 bits)
SEG1-
SEG312
Segment
driver
Grayscale palette (GSP)
<R>
<G>
<B>
16-grayscale control circuit
Power-supply
regulator
Window cursor control
Drive bias controller
Contrast
adjuster
VTEST
+ –
+ –
+ –
+ –
+ –
VR
VLPS
R
R
R
0
R
R
OPOFF
V1OUT
V2OUT
V3OUT
V4OUT
V5OUT
GND
4
HD66760
HD66760 Pad Arrangement
SEG2
SEG1
COM40
COM39
COM10
COM9
SEG18
SEG17
No.500
dummy1
COM8
No.449
dummy33
SEG19
SEG20
No.450
No.501
•
Chip size: 14.4 mm
×
3.1 mm
•
Chip thickness: 550
µm
(typ.)
•
PAD coordinates: PAD center
•
Coordinate origin: Chip center
•
Au bump size (pin number is shown
in the blacket)
(1) 80
µm ×
80
µm
dummy1 (500), dummy31 (121),
dummy32 (172) and dummy33 (449)
from C6 + (1) to dummy30 (112)
(2) 35
µm ×
80
µm
from SEG294 (173) to SEG19 (448)
(3) 80
µm ×
35
µm
from COM49 (122) to SEG295 (171)
from SEG18 (450) to COM9 (499)
(4) 45
µm ×
80
µm
from COM8 (501) to COM1 (508)
from COM41 (113) to COM48 (120)
•
Au bump pitch: Refer PAD coordinate
•
Au bump height: 15
µm
(typ.)
COM1
C6+
C6-
C5+
C5-
C4+
C4-
C3+
C3-
C2+
C2-
C1+
C1-
GNDDUM1
VLOUT
VLOUT
VLOUT
VLPS
VLPS
VLPS
VL1REF
VLREF
V1REF
V1OUT
V2OUT
V3OUT
V4OUT
V5OUT
Vci
Vci
Vci
Vci
Vci
dummy2
dummy3
No.448
No.508
No.1
No.2
dummy14
dummy15
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
GND
GND
GND
GND
GND
GND
GND
VTEST
VREG
VSW1
VSW2
GNDDUM2
TEST
OPOFF
VccDUM1
RESET*
CS*
RS
GNDDUM3
VccDUM2
IM0/ID
GNDDUM4
IM1
IM2
RW/RD*/SDA
E/WR*/SCL
GNDDUM5
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
OSC1
OSC2
dummy16
dummy17
HD66760
(Top view)
Y
X
dummy29
dummy30
COM41
No.120
No.173
SEG293
SEG294
COM48
dummy31
No.122
No.171
dummy32
SEG311
SEG312
COM80
COM79
COM50
COM49
SEG295
SEG296
No.121
No.172
5
stm32/stm8
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