based on 32Mx8 SDRAM with LVTTL, 4 banks & 8K Refresh
HYM72V64656B(L)T8 Series
DESCRIPTION
The HYM72V64656B(L)T8 H-series are high speed 3.3-Volt synchronous dynamic RAM Modules composed of sixteen
32Mx8 bit Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit EEPROM on a 168-pin glass-epoxy printed
circuit board. One 0.33mF and one 0.1mF decoupling capacitors per each SDRAM are mounted on the module.
The HYM72V64656B(L)T8 H-series are gold plated socket type Dual In-line Memory Modules suitable for easy inter-
change and addition of 512M bytes memory. All addresses, data and control inputs are latched on the rising edge of the
master clock input. The data paths are internally pipelined to achieve very high bandwidths.
FEATURES
• 1.15(29.21mm) PCB Height
• 168-Pin Unbuffered DIMM with Double Sided
• One 0.33mF and one 0.1mF decoupling capaci-
tors adopted
• Serial Presence Detect with Serial E
2
PROM
• Meets all the other JEDEC specifications
• Single 3.3V±0.3V power supply
• All device pins are LVTTL compatible
• 8192 refresh cycles / 64ms
• Fully synchronous ; all inputs referenced to posi-
tive edge of system clock
• Quad internal banks with single pulsed /RAS
• Auto precharge/precharge all banks by A
10
flag
• Possible to assert random column address every
•
•
•
•
•
•
•
•
clock cycle
Interleaved auto refresh mode
Programmable burst lengths and sequences
- 1,2,4,8,full page for Sequential type
- 1,2,4,8 for Interleave type
Programmable /CAS latency ; 2,3 clocks
Support clock suspend/power down mode by
CKE0, CKE1
Data mask function by DQM
Mode register set programming
Burst termination command
Self refresh provides minimum power, full internal
refresh control
ORDERING INFORMATION
Part No.
HYM72V64656BT8-P
HYM72V64656BT8-S
HYM72V64656BLT8-P
HYM72V64656BLT8-S
Clock
Frequency
100MHz
100MHz
100MHz
100MHz
Internal
Bank
Ref.
Power
Normal
SDRAM
Package
Plating
4 Banks
8K
Low Power
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.4/Jul. 02
1
PC100 SDRAM Unbuffered DIMM
HYM72V64656B(L)T8 Series
PIN DESCRIPTION
PIN
CK0~CK3
CKE0,CKE1
/S0~/S3
BA0, BA1
A0 ~ A12
/RAS, /CAS, /WE
DQM0~DQM7
DQ0 ~ DQ63
VCC
V
SS
SCL
SDA
SA0~2
WP
NC
PIN NAME
Clock Inputs
Clock Enable
Chip Select
SDRAM Bank Address
Address
Row Address Strobe, Column
Address Strobe, Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply (3.3V)
Ground
SPD Clock Input
SPD Data Input/Output
SPD Address Input
Write Protect for SPD
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
实时操作系统RTOS
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