Standard Products
TAQ8100
Telemetry Acquisition Controller
Radiation Hardened
www.aeroflex.com/RADHardTAQ
ADVANCED
October 4, 2007
DESCRIPTION
Aeroflex’s TAQ8100 is a radiation hardened,
programmable telemetry and control IC providing
up to 56-channels of analog telemetry reporting.
Data is accessed via the standard MIL-STD-1553B
serial data bus. This allows for simple and fast
integration with mission specific instrumentation.
The TAQ8100 has been specifically designed to meet exposure to radiation environments. The device is
available in a 256-lead High Temperature Co-fired Ceramic (HTCC) Quad Flatpack (CQFP) and is
guaranteed operational from -55°C to +125°C. Available screened in accordance with MIL-PRF-38535,
the TAQ8100 is ideal for demanding military and space applications.
KEY FEATURES
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Radiation performance
- Total dose
≥
100 krads(Si)
- LET, no latchup
≥
128 MeV-cm
2
/mg
MIL-STD-1553B interface
Low power consumption < 500mW
Customizable via firmware PROM
A/D Controller
- Controls up to 56 channels at 12-bit
resolution
- Internal two point calibration algorithm for
high accuracy
- Measurements updated every 20ms
Pulse Width Modulator (PWM)
- 24MHz resolution
- 8-bit frequency control (93.75KHz minimum)
- 8-bit phase control
❑
Digital Phase Locked Loop (DPLL)
- 24MHz resolution
- 5ms – 655ms selectable time constant
- Programmable lock range (50-200KHz typ)
- 100KHz starting frequency
16-bit GPIO Port
Serial Interface for access to internal RAM
Full military temperature range
Designed for aerospace and high reliability
space applications
Packaging – Hermetic CQFP
- 256 Leads, 1.46"Sq x .13"Ht
DSCC SMD Pending
Note: Aeroflex Plainview does not currently have
a DSCC certified Radiation Hardened Assurance
Program.
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❑
❑
❑
❑
❑
JTAG I / F
UT28F256QLT
PROM
JTAG I / F
A/D I/F
SμMMIT
1553 RT
TAQ8100
TELEMETRY
CONTROLLER
ASIC
PWM I/F
DPLL I/F
GPIO
1553B
SERIAL I/F
Figure 1 – System Diagram
SCD8100 Rev B
Advanced
10/4/07
Targeted Applications
The Aeroflex TAQ8100 is a control device used for high reliability, radiation-hardened space-qualified data acquisition and
telemetry. Up to 56 analog voltages may be digitized with 12-bit accuracy and transmitted on a MIL-STD-1553B
communications bus.
Interface and control signals are provided for a 12-bit A/D Converter and a 56-input Analog Multiplexer. In a typical
application, 48 Mux inputs are used for external inputs and 8 Mux inputs are used for reference voltage and other special
inputs.
The TAQ8100 includes a Phase Lock Loop (PLL) which generates Modulator and Demodulator clocks that are used to
implement transformer-coupled isolation circuits. This feature allows the measurement of floating analog input voltages
which are referenced to a return that is electrically isolated from the A/D Converter and the TAQ8100 itself.
The TAQ8100 is designed to operate with the Aeroflex SμMMIT (Serial, μcoded, Monolithic, Multi-Mode, Intelligent
Terminal), which provides interfacing to the 1553B bus.
The TAQ8100 includes a processing algorithm that uses slope and offset correction of potential errors in the A/D and Mux
circuits. The circuit achieves a measurement error of less than 10mV over a 16.5 year life in a 100KRad total dose
radiation environment. With a voltage input range of 5 volts, this is a conversion accuracy of better than 0.2% of full scale.
The TAQ8100 also provides three discrete outputs. The Low Input discrete indicates that one of the analog inputs has
dropped below a preset value. The High Input discrete indicates that an input has exceeded a different preset value. The
Alarm discrete indicates that an input has exceeded a third discrete value (Typically, the Alarm threshold is set higher than
the High Input threshold). Once set, the Alarm discrete remains latched until reset by either a 1553B command or by the
removal of power.
An external PROM provides user-definable configuration parameters, including the threshold values for Low Input, High
Input and Alarm, and preset conditions for the PLL.
CONTROL CIRCUIT
ALARM
(Discrete)
HIGH INPUT
(Discrete)
LOW INPUT
(Discrete)
1553B
Channel A
1553B
Channel B
XFMR
SμMMIT
1553 RT
XFMR
DEMOD
MOD
A/D
12-BIT
12
DEMOD
MUX
56
CHANNEL
MOD
TAQ8100
ASIC
PLL
CLOCK
DRIVER
DEMOD
MOD
DEMOD
PROM
MOD
ON
OFF
RELAY
PRECISION
REFERENCE
4.000V
DEMOD
MOD
+30 VDC
POWER
SUPPLY
+12VDC
(ISOLATED)
+5VDC
-12VDC
+12VDC
⎫
⎬
⎭
FLOATING
INPUT
(UP to 48)
CLOCK FEEDBACK
DEMOD CLOCK
MOD CLOCK
POWER SUPPLY GROUND
FLOATING
INPUT
RETURN
Typical Application
Analog Data Acquisition with Floating Analog Inputs
SCD8100 Rev B
Advanced
10/4/07
2
Aeroflex Plainview
The Aeroflex Rad Hard Programmable Control & Telemetry Chipset is comprised of the
following devices:
Aeroflex TAQ8100 Telemetry Control
Aeroflex UT69151DXE SμMMIT 1553 Remote Terminal
Aeroflex UT28F256QLT PROM
Aeroflex ACT8501 Analog Mux
Operating Features
A programmable sequencer state machine in the TAQ8100 customizes the chip functionality using firmware to set any
configuration of 1553 sub-addresses for telemetry and control command. Many of the TAQ8100 hardware modules
contain programmable registers, which can also be controlled via firmware.
A/D Controller
The main function of the chip is the reporting of spacecraft telemetry via 1553. The TAQ8100 interfaces directly to a 12-bit
flash A/D converter such as the HMXADC9225 or AD9225 using a set of industry standard analog multiplexers. The A/D
converter can be used to measure up to 56-channels. The TAQ8100 provides all of the necessary digital chip select and
addressing control signals for the multiplexers.
The A/D controller changes the input channel every 220μS. Each sample is read by the TAQ8100 at 110μS following an
address change to allow settling time for the signal. For added noise immunity, eight samples are taken at 10μS intervals
and averaged. All of the samples are stored in TAQ8100 RAM, ready for retrieval via 1553 at any time with the entire
process repeated every 20ms.
For highest accuracy, the TAQ8100 employs a two-point calibration technique using two fixed reference voltages, 4V and
0V. This cancels out any gain and offset errors which may be present in the system.
GPIO Port
The TAQ8100 contains a 16-bit GPIO (General Purpose Input / Output) port which is controlled and read by firmware. Half
of the port is compatible with CMOS logic levels while the other half is compatible with TTL logic levels.
Serial Port
The TAQ8100's 2Kx16 internal RAM, the external 4Kx8 PROM and the SμMMIT control registers can be accessed for read
and write operations via a full duplex serial port.
JTAG
The TAQ8100 contains an IEEE 1149.1 compliant JTAG ports for boundary scan. The BSDL file is available.
Internal Functions
Pulse Width Modulator
The PWM (Pulse Width Modulation) module in the TAQ8100 can generate pulses with firmware controllable period and
width. PWM timing is based on an internal 24MHz clock developed from the input 48MHz clock signal. The PWM period
can be set from 4 to as many as 256 clock cycle durations at the 24MHz clock frequency. This results in a 93.75KHz
minimum frequency (24MHz / 256 = 93.75KHz) and pulse widths which can be any integer number of 24MHz clock cycles
at 41.667nS step size.
DPLL
The DPLL (Digital Phase Locked Loop) creates two frequency locked clock outputs, one at 50% duty cycle and the other
with a programmable phase and duty cycle. The clocks start out at 100KHz and will lock to an active high feedback pulse
which is expected to be centered in the phase where the 50% duty cycle output clock is low. The tracking range of the
PLL is programmable and is typically 50KHz to 200KHz. The loop employs a single pole digital IIR low pass filter with a
selectable time constant between 5mS and 655mS. The hardware is also insensitive to any chatter that may be present
on the feedback pulse, as only the first edge detected is used.
SCD8100 Rev B
Advanced
10/4/07
3
Aeroflex Plainview
I/O Signal Description
Name
Pin
Description
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A2D_CLK
A2D_D11
A2D_D10
A2D_D9
A2D_D8
A2D_D7
A2D_D6
A2D_D5
A2D_D4
A2D_D3
A2D_D2
A2D_D1
A2D_D0
ARM_CLK
ARM_DATA
ARM_MON_CLK
ARM_MON_DATA
ARM_MON_SHIFT
ARM_OE
BAL_CLK
BYPASS_CLK
BYPASS_DATA
BYPASS_OE
CLK48MHZ
CSREGS
D15
D14
D13
D12
D11
SCD8100 Rev B
Advanced
10/4/07
54
53
52
51
48
47
46
45
44
41
40
39
227
230
231
232
233
236
237
238
239
240
241
242
243
179
178
183
188
182
177
118
174
173
172
71
27
3
4
5
6
7
Address bus MSB
Address bus bit
Address bus bit
Address bus bit
Address bus bit
Address bus bit
Address bus bit
Address bus bit
Address bus bit
Address bus bit
Address bus bit
Address bus LSB
1-MHz clock to A/D
A/D data MSB
A/D data bit
A/D data bit
A/D data bit
A/D data bit
A/D data bit
A/D data bit
A/D data bit
A/D data bit
A/D data bit
A/D data bit
A/D data LSB
100-KHz clock to Arm shift registers
Serial data to Arm shift registers
1-MHz clock to Arm monitor shift registers
Serial data from arm monitor shift registers
Load/shift control to Arm monitor registers
Active high Output enable to Arm registers
50% Duty Cycle Balancing Clock
100-KHz clock to bypass shift registers
Serial data to bypass registers
Active high output enable to bypass registers
48-MHz clock input
Chip Select to access SuMMIT registers
Data bus MSB
Data bus bit
Data bus bit
Data bus bit
Data bus bit
4
Aeroflex Plainview
I/O Signal Description (con’t)
Name
Pin
Description
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DMAR
DMAG
DMACK
DTACK
FB
GPIO_15
GPIO_14
GPIO_13
GPIO_12
GPIO_11
GPIO_10
GPIO_9
GPIO_8
GPIO_7
GPIO_6
GPIO_5
GPIO_4
GPIO_3
GPIO_2
GPIO_1
GPIO_0
HIGH_CELL
LOW_CELL
MASTER_PWR_ON
MASTER_RLY_PWR
MON_CLK
MUX_ADDR0
MUX_ADDR1
MUX_ADDR2
MUX_CS0
10
11
12
13
14
17
18
19
20
21
24
33
28
32
29
112
88
89
90
91
94
95
96
97
100
101
102
103
104
105
108
109
79
80
190
185
115
219
220
221
208
Data bus bit
Data bus bit
Data bus bit
Data bus bit
Data bus bit
Data bus bit
Data bus bit
Data bus bit
Data bus bit
Data bus bit
Data bus LSB
DMA request, active low
DMA grant, active low
DMA acknowledge, active low
Data Transfer Acknowledge, active low
Feedback pulse from balancer for PLL
GPIO port (input only)
GPIO port
GPIO port
GPIO port
GPIO port
GPIO port
GPIO port
GPIO port
GPIO port
GPIO port
GPIO port
GPIO port
GPIO port
GPIO port
GPIO port
GPIO port
High cell indicator, active high
Low cell indicator, active high
Master relay power on indicator, active high
Master relay power on control, active high
Monitor clock for cell voltage sampling
Analog Mux address LSB
Analog Mux address bit
Analog Mux address MSB
Analog Mux Chip Select, active low
SCD8100 Rev B
Advanced
10/4/07
5
Aeroflex Plainview
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