HY57V643220D(L/S)T(P)-xI Series
4Banks x 512K x 32bits Synchronous DRAM
Document Title
4Bank x 512K x 32bits Synchronous DRAM
Revision History
Revision
No.
0.1
0.2
0.3
0.4
Initial Draft
Removed Preliminary
1. Updated Output Load Capacitance for Access Time Measurement CL = 30pF in
AC OPERATING TEST CONDITION
2. Updated the tolerance zone of the leads and the description of the package type
in PACKAGE DIMENSION
1.Corrected : Lead range tolerance (Page : 13)
History
Draft Date
June. 2004
July 2004
Sep. 2004
Sep. 2005
Remark
Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.4 / Sep. 2005
1
HY57V643220D(L/S)T(P)-xI Series
4Banks x 512K x 32bits Synchronous DRAM
DESCRIPTION
The Hynix HY57V643220D(L/S)T(P)-xI series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications
which require wide data I/O and high bandwidth. HY57V643220D(L/S)T(P)-xI is organized as 4banks of 524,228x32.
HY57V643220D(L/S)T(P)-xI is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All
input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)
FEATURES
•
•
•
Voltage : VDD, VDDQ 3.3V supply voltage
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 86pin TSOP-II with 0.5mm of pin
pitch
All inputs and outputs referenced to positive edge of sys-
tem clock
Data mask function by DQM 0, 1, 2 and DQM 3
Internal four banks operation
•
•
•
•
•
Auto refresh and self refresh
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
•
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
Burst Read Single Write operation
•
•
ORDERING INFORMATION
Part No.
HY57V643220D(L/S)T(P)-45I
6)
HY57V643220D(L/S)T(P)-5I
6)
HY57V643220D(L/S)T(P)-55I
6)
HY57V643220D(L/S)T(P)-6I
6)
HY57V643220D(L/S)T(P)-7I
6)
Note
1. HY57V643220DT(P)-xI
2. HY57V643220DLT(P)-xI
3. HY57V643220DST(P)-xI
4. HY57V643220D(L/S)T-xI
5. HY57V643220D(L/S)TP-xI
Series : Normal Power
Series : Low Power
Series : Super Low Power
Series : Leaded
Series : Lead Free
Clock
Frequency
222MHz
200MHz
183MHz
166MHz
143MHz
4Banks x 512Kbits x32
LVTTL
86pin TSOP-II
Organization
Interface
Package
6. I : Industrial Temperature (-40
o
C ~ 85
o
C)
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.4 / Sep. 2005
2
HY57V643220D(L/S)T(P)-xI Series
4Banks x 512K x 32bits Synchronous DRAM
Pin FUNCTION DESCRIPTIONS
Pin
CLK
Clock
Pin Name
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
CKE
CS
BA0, BA1
Clock Enable
Chip Select
Bank Address
A0 ~ A10
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
VDD/VSS
VDDQ/VSSQ
NC
Rev. 0.4 / Sep. 2005
4
FPGA/CPLD
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