HY62V8100A-(I)/HY62U8100A-(I) Series
128Kx8bit CMOS SRAM
DESCRIPTION
The HY62V8100A-(I)/HY62U8100A-(I) is a high
speed, low power and 1M bit CMOS SRAM
organized as 131,072 words by 8bit. The
HY62V8100A-(I) / HY62U8100A-(I) uses high
performance CMOS process technology and
designed for high speed low power circuit
technology. It is particulary well suited for used in
high density low power system application. This
device has a data retention mode that guarantees
data to remain valid at a minimum power supply
voltage of 2.0V.
FEATURES
•
Fully static operation and Tri-state output
•
TTL compatible inputs and outputs
•
Battery backup(L/LL-part)
- 2.0V(min) data retention
•
Standard pin configuration
- 32pin 8x20mm/ 8x13.4mm Small TSOP-I
(Standard and Reversed)
Product
Voltage
Speed
Operation
Standby Current(uA)
No.
(V)
(ns)
Current(mA)
L
LL
HY62V8100A
3.3
85/100/120
5
50
10
HY62V8100A-I
3.3
85/100/120
5
50
20
HY62U8100A
3.0
100/120/150
5
50
10
HY62U8100A-I
3.0
100/120/150
5
50
15
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature
2. Current value is max.
Temperature
(°C)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
PIN CONNECTION
A11
A9
A8
A13
/WE
CS2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CS1
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A1
A2
A3
A4
A5
A6
A7
A12
A14
A16
NC
Vcc
A15
CS2
/WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
DQ4
DQ5
DQ6
DQ7
DQ8
/CS1
A10
/OE
TSOP-I/Small TSOP-I
(Standard)
TSOP-I/Small TSOP-I
(Reversed)
PIN DESCRIPTION
Pin Name
/CS1
CS2
/WE
/OE
A0 ~ A16
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Chip Select 1
Chip Select 2
Write Enable
Output Enable
Address Input
Data Input/Output
Power(3.3V or 3.0V)
Ground
A0
ADD INPUT BUFFER
BLOCK DIAGRAM
SENSE AMP
ROW DECODER
COLUMN DECODER
I/O1
OUTPUT BUFFER
I/O8
A16
CONTROL
LOGIC
/CS1
CS2
/OE
/WE
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.06 /Jan.99
Hyundai Semiconductor
WRITE DRIVER
MEMORY ARRAY
1024x1024
HY62V8100A-(I)/HY62U8100A-(I) Series
ORDERING INFORMATION
Part No.
HY62V8100ALT1
HY62V8100ALLT1
HY62V8100ALR1
HY62V8100ALLR1
HY62V8100ALST
HY62V8100ALLST
HY62V8100ALSR
HY62V8100ALLSR
HY62V8100ALT1-I
HY62V8100ALLT1-I
HY62V8100ALR1-I
HY62V8100ALLR1-I
HY62V8100ALST-I
HY62V8100ALLST-I
HY62V8100ALSR-I
HY62V8100ALLSR-I
HY62U8100ALT1
HY62U8100ALLT1
HY62U8100ALR1
HY62U8100ALLR1
HY62U8100ALST
HY62U8100ALLST
HY62U8100ALSR
HY62U8100ALLSR
HY62U8100ALT1-I
HY62U8100ALLT1-I
HY62U8100ALR1-I
HY62U8100ALLR1-I
HY62U8100ALST-I
HY62U8100ALLST-I
HY62U8100ALSR-I
HY62U8100ALLSR-I
Speed
85/100/120
85/100/120
85/100/120
85/100/120
85/100/120
85/100/120
85/100/120
85/100/120
85/100/120
85/100/120
85/100/120
85/100/120
85/100/120
85/100/120
85/100/120
85/100/120
100/120/150
100/120/150
100/120/150
100/120/150
100/120/150
100/120/150
100/120/150
100/120/150
100/120/150
100/120/150
100/120/150
100/120/150
100/120/150
100/120/150
100/120/150
100/120/150
Power
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
Temp.
Package
TSOP-I(Standard)
TSOP-I(Standard)
TSOP-I(Reversed)
TSOP-I(Reversed)
Small TSOP-I(Standard)
Small TSOP-I(Standard)
Small TSOP-I(Reversed)
Small TSOP-I(Reversed)
TSOP-I(Standard)
TSOP-I(Standard)
TSOP-I(Reversed)
TSOP-I(Reversed)
Small TSOP-I(Standard)
Small TSOP-I(Standard)
Small TSOP-I(Reversed)
Small TSOP-I(Reversed)
TSOP-I(Standard)
TSOP-I(Standard)
TSOP-I(Reversed)
TSOP-I(Reversed)
Small TSOP-I(Standard)
Small TSOP-I(Standard)
Small TSOP-I(Reversed)
Small TSOP-I(Reversed)
TSOP-I(Standard)
TSOP-I(Standard)
TSOP-I(Reversed)
TSOP-I(Reversed)
Small TSOP-I(Standard)
Small TSOP-I(Standard)
Small TSOP-I(Reversed)
Small TSOP-I(Reversed)
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
Note 1. E.T. : Extended Temperature, Blank : Normal Temperature
ABSOLUTE MAXIMUM RATING (1)
Symbol
Vcc, V
IN,
V
OUT
T
A
Parameter
Power Supply, Input/Output Voltage
Operating Temperature
Rating
-0.3 to 4.6
0 to 70
-40 to 85
T
STG
P
D
I
OUT
T
SOLDER
Storage Temperature
Power Dissipation
Data Output Current
Lead Soldering Temperature & Time
-65 to 125
1.0
50
260
•
10
Unit
V
°C
°C
°C
W
mA
°C•sec
Remark
HY62V8100A
HY62U8100A
HY62V8100A-I
HY62U8100A-I
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
Rev.06 /Jan.99
2
HY62V8100A-(I)/HY62U8100A-(I) Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Product
HY62V8100A-(I)
HY62U8100A-(I)
HY62V8100A-(I)
HY62U8100A-(I)
HY62V8100A-(I)
HY62U8100A-(I)
HY62V8100A-(I)
HY62U8100A-(I)
Min.
3.0
2.7
0
2.2
-0.3
(1)
Typ.
3.3
3.0
0
-
-
Max.
3.6
3.3
0
Vcc+0.3
0.6
Unit
V
V
V
V
V
Note :
1. V
IL
= -1.5V for pulse width less than 30ns
TRUTH TABLE
/CS1
H
X
L
L
L
CS2
X
L
H
H
H
/WE
X
X
H
H
L
/OE
X
X
H
L
X
MODE
Standby
Output Disabled
Read
Write
I/O OPERATION
High-Z
High-Z
High-Z
Data Out
Data In
Note :
1. H=V
IH
, L=V
IL
, X=don't care
DC ELECTRICAL CHARACTERISTICS
Vcc = 3.3V±10%/3.0V±10%, T
A
= 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
-1
-
1
uA
-1
-
1
uA
I
LO
Output Leakage Current
Vss <V
OUT
< Vcc, /CS1 = V
IH
or
CS2 = V
IL
or
/
OE
=
V
IH
or /WE =
V
IL
Icc
Operating Power Supply
/CS1 = V
IL
, CS2 = V
IH,
-
3
5
mA
Current
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
I
CC1
Average
HY62V8100A-(I) /CS1 = V
IL
CS2 = V
IH,
-
25
35
mA
Operating HY62U8100A-(I) Min Duty Cycle = 100%, I
I/O =
0mA
-
20
30
mA
Current
I
SB
TTL Standby Current
/CS1 = V
IH
or CS2 = V
IL
-
-
0.5
mA
(TTL Input)
I
SB1
Standby
HY62V8100A
/CS1 > Vcc - 0.2V
L
-
1
50
uA
Current
CS2 < 0.2V or
LL
-
0.5
10
uA
(CMOS
HY62V8100A-I
CS2 > Vcc - 0.2V
L
-
1
50
uA
Input)
LL
-
0.5
20
uA
HY62U8100A
L
-
1
50
uA
LL
-
0.5
10
uA
HY62U8100A-I
L
-
1
50
uA
LL
-
0.5
15
uA
V
OL
Output Low Voltage
I
OL
= 2.1mA
-
-
0.4
V
V
OH
Output High Voltage
I
OH =
-1mA
2.2
-
-
V
Note : Typical values are at Vcc = 3.3V/3.0V, T
A
= 25°C
Rev.06 /Jan.99
3
HY62V8100A-(I)/HY62U8100A-(I) Series
AC CHARACTERISTICS(I)
Vcc = 3.3V±10%, T
A
= 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
-85
-10
-12
# Symbol
Parameter
Min.
Max. Min.
Max. Min
Max.
READ CYCLE
1
tRC
Read Cycle Time
85
-
100
-
120
-
2
tAA
Address Access Time
-
85
-
100
-
120
3
tACS
Chip Select Access Time
-
85
-
100
-
120
4
tOE
Output Enable to Output Valid
-
45
-
50
-
60
5
tCLZ
Chip Select to Output in Low Z
10
-
10
-
20
-
6
tOLZ
Output Enable to Output in Low Z
5
-
5
-
10
-
7
tCHZ
Chip Deselection to Output in High Z
0
30
0
30
0
40
8
tOHZ
Out Disable to Output in High Z
0
30
0
30
0
40
9
tOH
Output Hold from Address Change
10
-
10
-
20
-
WRITE CYCLE
10 tWC
Write Cycle Time
85
-
100
-
120
-
11 tCW
Chip Selection to End of Write
70
-
80
-
100
-
12 tAW
Address Valid to End of Write
70
-
80
-
100
-
13 tAS
Address Set-up Time
0
-
0
-
0
-
14 tWP
Write Pulse Width
55
-
60
-
85
-
15 tWR
Write Recovery Time
0
-
0
-
0
-
16 tWHZ
Write to Output in High Z
0
30
0
30
0
50
17 tDW
Data to Write Time Overlap
40
-
45
-
50
-
18 tDH
Data Hold from Write Time
0
-
0
-
0
-
19 tOW
Output Active from End of Write
5
-
5
-
5
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC CHARACTERISTICS(II)
Vcc = 3.0V±10%, T
A
= 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
-10
-12
-15
# Symbol
Parameter
Min.
Max. Min.
Max. Min
Max.
READ CYCLE
1
tRC
Read Cycle Time
100
-
120
-
150
-
2
tAA
Address Access Time
-
100
-
120
-
150
3
tACS
Chip Select Access Time
-
100
-
120
-
150
4
tOE
Output Enable to Output Valid
-
50
-
60
-
75
5
tCLZ
Chip Select to Output in Low Z
20
-
20
-
20
-
6
tOLZ
Output Enable to Output in Low Z
10
-
10
-
10
-
7
tCHZ
Chip Deselection to Output in High Z
0
30
0
40
0
50
8
tOHZ
Out Disable to Output in High Z
0
30
0
40
0
50
9
tOH
Output Hold from Address Change
20
-
20
-
20
-
WRITE CYCLE
10 tWC
Write Cycle Time
100
-
120
-
150
-
11 tCW
Chip Selection to End of Write
80
-
100
-
120
-
12 tAW
Address Valid to End of Write
80
-
100
-
120
-
13 tAS
Address Set-up Time
0
-
0
-
0
-
14 tWP
Write Pulse Width
75
-
85
-
100
-
15 tWR
Write Recovery Time
0
-
0
-
0
-
16 tWHZ
Write to Output in High Z
0
35
0
40
0
50
17 tDW
Data to Write Time Overlap
45
-
50
-
60
-
18 tDH
Data Hold from Write Time
0
-
0
-
0
-
19 tOW
Output Active from End of Write
10
-
10
-
10
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.06 /Jan.99
4
HY62V8100A-(I)/HY62U8100A-(I) Series
AC TEST CONDITIONS
T
A
= 0°C to 70°C (Normal) / -40°C to 85°C (E.T.), unless otherwise specified
PARAMETER
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
1.5V
Output Load
CL = 100pF + 1TTL Load
AC TEST LOADS
TTL
CL(1)
Note : 1 Including jig and scope capacitance
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol
Parameter
C
IN
Input Capacitance
C
OUT
Output Capacitance
Condition
V
IN
= 0V
V
I/O
= 0V
Max.
6
8
Unit
pF
pF
Note : These parameters are sampled and not 100% tested
TIMING DIAGRAM
READ CYCLE 1
tRC
ADDR
tAA
OE
tOE
tOLZ
CS1
tOH
CS2
tACS
tCLZ
Data
Out
High-Z
Data Valid
tOHZ
tCHZ
Rev.06 /Jan.99
5
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