M65608E
128 K
8 Very Low Power CMOS SRAM Rad Tolerant
Introduction
The M65608E is a very low power CMOS static RAM
organized as 131072
×
8 bits.
TEMIC brings the solution to applications where fast
computing is as mandatory as low consumption, such as
aerospace electronics, portable instruments, or
embarked systems.
Utilizing an array of six transistors (6T) memory cells,
the M65608E combines an extremely low standby
supply current (Typical value = 0.2
µA)
with a fast
access time at 30 ns over the full military temperature
range. The high stability of the 6T cell provides
excellent protection against soft errors due to noise.
The M65608E is processed according to the methods of
the latest revision of the MIL STD 883 (class B or S),
ESA SCC 9000 or QML.
Features
D
Access time: 30, 45 ns
D
Very low power consumption
active : 250 mW (Typ)
standby : 1
µW
(Typ)
data retention : 0.5
µW
(Typ)
D
Wide temperature Range : –55 To +125°C
D
400 Mils width package
D
D
D
D
D
TTL compatible inputs and outputs
Asynchronous
Single 5 volt supply
Equal cycle and access time
Gated inputs :
no pull-up/down
resistors are required
Interface
Block Diagram
Rev. E – June 5, 2000
1
M65608E
Pin Configuration
32 pins DIL side-brazed
32 pins Flatpack
400 MILS
400 MILS
Pin Names
A0–A16
I/O0–I/O7
CS
1
CS
2
W
OE
V
CC
GND
Address inputs
Data Input/Output
Chip select 1
Chip select 2
Write Enable
Output Enable
Power
Ground
Truth Table
CS
1
H
X
L
L
L
CS
2
X
L
H
H
H
W
X
X
H
L
H
OE
X
X
L
X
H
INPUTS/
OUTPUTS
Z
Z
Data Out
Data In
Z
MODE
Deselect/
Power-down
Deselect/
Power Down
Read
Write
Output Disable
L = low, H = high, X = H or L, Z = high impedance.
2
Rev. E – June 5, 2000
M65608E
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : . . . . . . . . . . . . . . . - 0.5 V + 7.0 V
DC input voltage : . . . . . . . . . . . . . . . . . GND – 0,3 V to VCC + 0,3
DC output voltage high Z state : . . . . . . GND – 0,3 V to VCC + 0,3
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . –65
°C
to + 150
°C
Output current into outputs (low) : . . . . . . . . . . . . . . . . . . . . . . 20 mA
Electro statics discharge voltage : . . . . . . . . . . . . . . . . . . . > 2 001 V
(MIL STD 883D method 3015.3)
Operating Range
OPERATING VOLTAGE
Military
5 V
±
10 %
OPERATING TEMPERATURE
– 55
_C
to + 125
_C
Recommended DC Operating Conditions
PARAMETER
Vcc
Gnd
VIL
VIH
DESCRIPTION
Supply voltage
Ground
Input low voltage
Input high voltage
MINIMUM
4.5
0.0
GND – 0.3
2.2
TYPICAL
5.0
0.0
0.0
–
MAXIMUM
5.5
0.0
0.8
V
CC
+ 0.3
UNIT
V
V
V
V
Capacitance
PARAMETER
Cin (1)
Cout (1)
Note :
DESCRIPTION
Input low voltage
Output high volt
MINIMUM
–
–
TYPICAL
–
–
MAXIMUM
8
8
UNIT
pF
pF
1. Guaranteed but not tested.
DC Parameters
PARAMETER
IIX (2)
IOZ (2)
VOL (3)
VOH (4)
Notes :
DESCRIPTION
Input leakage current
Output leakage current
Output low voltage
Output high voltage
MINIMUM
–1
–1
–
2.4
TYPICAL
–
–
–
–
MAXIMUM
1
1
0.4
–
UNIT
µA
µA
V
2. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output Disabled.
3. Vcc min. IOL = 8.0 mA.
4. Vcc min. IOH = –4.0 mA.
Rev. E – June 5, 2000
3
M65608E
Consumption
SYMBOL
ICCSB (5)
ICCSB
1
(6)
ICCOP (7)
Notes :
DESCRIPTION
Standby supply current
Standby supply current
Dynamic operating current
65608
– 30
2
300
130
65608
– 45
2
300
100
UNIT
mA
µA
mA
VALUE
max
max
max
5. CS
1
≥
VIH or CS
2
≤
VIL and CS
1
≤
VIL.
6. CS
1
≥
Vcc – 0.3 V or, CS
2
< Gnd + 0.3 V and CS
1
≤
0.2 V
7. F = 1/TAVAV, Iout = 0 mA, W = OE = VIH, Vin = Gnd/Vcc, Vcc max.
AC Parameters
Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V
Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output loading IOL/IOH (see figure 1a and 1b) : . . . . . . . . . + 30 pF
AC Test Loads Waveforms
Figure 1a
Figure 1b
Figure 2
Data Retention Mode
MHS CMOS RAM’s are designed with battery backup
in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure
data retention :
1. . During data retention chip select CS
1
must be held
high within VCC to VCC -0.2 V or, chip select CS
2
must be held low within GND to GND + 0.2 V.
2. Output Enable (OE) should be held high to keep the
RAM outputs high impedance, minimizing power
dissipation.
3. During power up and power down transitions CS
1
and OE must be kept between VCC + 0.3 V and
70 % of VCC, or with CS
2
between GND and GND
- 0.3 V.
4. The RAM can begin operation > TR ns after Vcc
reaches the minimum operation voltages (4.5 V).
4
Rev. E – June 5, 2000
M65608E
Timing
Data Retention Characteristics
PARAMETER
VCCDR
TCDR
TR
ICCDR1 (10)
ICCDR2 (10)
Notes :
DESCRIPTION
Vcc for data retention
Chip deselect to data retention time
Operation recovery time
Data retention current @ 2.0 V
Data retention current @ 3.0 V
MINIMUM
2.0
0.0
TAVAV (9)
–
–
TYPICAL
T
A
= 25
_C
–
–
–
0.1
0.2
MAXIMUM
–
–
–
150
200
UNIT
V
ns
ns
µA
µA
9. TAVAV = Read cycle time.
10. CS
1
= Vcc or CS
2
= CS
1
= GND, Vin = Gnd/Vcc, this parameter is only tested at Vcc = 2 V.
Rev. E – June 5, 2000
5
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