HD74AC107/HD74ACT107
Dual JK Flip-Flop (with Separate Clear and Clock)
Description
The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop.
Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the
coupling transistors which connect the master and slave sections. The sequence of operation is as follows:
1) isolate slave from master; 2) enter information from J and K inputs to master; 3) disable J and K inputs;
4) transfer information from master to slave.
Features
•
Outputs Source/Sink 24 mA
•
HD74ACT107 has TTL-Compatible Inputs
Pin Arrangement
J
1
1
Q
1
2
Q
1
3
K
1
4
Q
2
5
Q
2
6
GND 7
(Top view)
14 V
CC
13
C
D1
12
CP
1
11 K
2
10
C
D2
9
CP
2
8 J
2
HD74AC107/HD74ACT107
Logic Symbol
3
8
9
Q
1
2
11
1
12
4
J
1
CP
1
K
1
Q
1
J
2
CP
2
K
2
Q
2
6
C
D1
13
C
D2
10
Q
2
5
V
CC
= Pin14
GND = Pin7
Pin Names
J
1
, J
2
, K
1
, K
2
CP
1
,
CP
2
C
D1
,
C
D2
Q
1
, Q
2
,
Q
1
,
Q
2
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active Low)
Outputs
Truth Table
Inputs
@ t
n
J
L
L
H
H
H
L
t
n
t
n + 1
:
:
:
:
K
L
H
L
H
High Voltage Level
Low Voltage Level
Bit time before clock pulse.
Bit time after clock pulse.
Outputs
@ t
n + 1
Q
Qn
L
H
Qn
2
HD74AC107/HD74ACT107
Logic Diagram
C
D
J
K
CP
#CP
CP
#CP
Q
#CP
#CP
Q
CP
CP
CP
CP
CP
DC Characteristics
(unless otherwise specified)
Item
Maximum quiescent supply current
Maximum quiescent supply current
Maximum additional I
CC
/input
(HD74ACT107)
Symbol
I
CC
I
CC
I
CCT
Max
80
8.0
1.5
Unit
µA
µA
mA
Condition
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = Worst case
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = 25°C
V
IN
= V
CC
– 2.1 V, V
CC
= 5.5 V
Ta = Worst case
3
HD74AC107/HD74ACT107
AC Characteristics: HD74AC107
Ta = +25°C
C
L
= 50 pF
Item
Maximum clock
frequency
Propagation delay
C
P
to Q or
Q
Propagation delay
C
P
to Q or
Q
Propagation delay
C
D
to
Q
Propagation delay
C
D
to
Q
Note:
t
PHL
t
PLH
t
PHL
t
PLH
Symbol
f
max
V
CC
(V)*
1
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
Min
125
150
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Typ
—
—
9.5
7.5
10.0
8.0
9.5
7.5
9.5
7.5
Max
—
—
13.0
10.0
13.5
10.5
13.0
10.0
13.0
10.0
Ta = –40°C to +85°C
C
L
= 50 pF
Min
100
125
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
—
—
14.0
11.0
14.5
11.5
14.0
11.0
14.0
11.0
ns
ns
ns
ns
Unit
MHz
Operating Requirements: HD74AC107
Ta = +25°C
C
L
= 50 pF
Item
Setup time
J or k to
C
P
Hold time
C
P
to J or k
Pulse width
C
P
or
C
D
Recovery time
C
D
to
C
P
Note:
t
rec
t
w
t
h
Symbol
t
su
V
CC
(V)*
1
Typ
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.0
2.0
–1.5
–0.5
2.0
2.0
–2.5
–1.5
Ta = –40°C
to +85°C
C
L
= 50 pF
Guaranteed Minimum
5.5
4.0
0.0
0.0
5.5
4.5
0.0
0.0
6.0
4.5
0.0
0.0
7.5
5.0
0.0
0.0
Unit
ns
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
4
HD74AC107/HD74ACT107
AC Characteristics: HD74ACT107
Ta = +25°C
C
L
= 50 pF
Item
Maximum clock
frequency
Propagation delay
C
P
to Q or
Q
Propagation delay
C
P
to Q or
Q
Propagation delay
C
D
to
Q
Propagation delay
C
D
to Q
Note:
Symbol
f
max
t
PLH
t
PHL
t
PLH
t
PHL
V
CC
(V)*
1
5.0
5.0
5.0
5.0
5.0
Min
100
1.0
1.0
1.0
1.0
Typ
—
9.5
10.5
8.5
8.5
Max
—
12.5
13.0
11.0
11.0
Ta = –40°C to +85°C
C
L
= 50 pF
Min
80
1.0
1.0
1.0
1.0
Max
—
13.5
14.0
12.0
12.0
Unit
MHz
ns
1. Voltage Range 5.0 is 5.0 V
±
0.5 V
Operating Requirements: HD74ACT107
Ta = +25°C
C
L
= 50 pF
Item
Setup time
J or k to
C
P
Hold time
C
P
to J or k
Pulse width
C
P
or
C
D
Recovery time
C
D
to
C
P
Note:
Symbol
t
su
t
h
t
w
t
rec
V
CC
(V)*
1
Typ
5.0
5.0
5.0
5.0
2.5
0.0
4.5
—
Ta = –40°C
to +85°C
C
L
= 50 pF
Guaranteed Minimum
7.0
1.5
7.0
3.0
8.0
1.5
8.0
3.0
Unit
ns
1. Voltage Range 5.0 is 5.0 V
±
0.5 V
Capacitance
Item
Input capacitance
Power dissipation capacitance
Symbol
C
IN
C
PD
Typ
4.5
35.0
Unit
pF
pF
Condition
V
CC
= 5.5 V
V
CC
= 5.0 V
5
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