Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . 300°C
Package Type
TO-99 (J)
8-Lead Hermetic DIP (Z)
8-Lead Plastic DIP (P)
8-Lead SO (S)
20-Contact LCC (RC)
JA
4
JC
ORDERING GUIDE
Model
OP97AZ
OP97ARC/883
2
OP97EJ
OP97EZ
OP97EP
OP97FJ
OP97FZ
OP97FP
OP97FS
OP97FS-REEL
OP97FS-REEL7
Temperature
Range
–55°C to +125°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package
Option
1
8-Pin Cerdip
20-Contact LCC
TO-99
8-Pin Cerdip
8-Pin Plastic DIP
TO-99
8-Pin Cerdip
8-Pin Plastic DIP
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
150
148
103
158
98
18
16
43
43
98
NOTES
1
For outline information see Package Information section.
2
For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory for /883 data sheet.
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
For supply voltages less than
±
20 V, the absolute maximum input voltage is equal
to the supply voltage.
3
The OP97’s inputs are protected by back-to-back diodes. Current-limiting resis-
tors are not used in order to achieve low noise. Differential input voltages greater
than 1 V will cause excessive current to flow through the input protection diodes
unless limiting resistance is used.
4
θ
JA
is specified for worst case mounting conditions, i.e.,
θ
JA
is specified for device
in socket for TO, cerdip, and P-DIP packages;
θ
JA
is specified for device soldered
to printed circuit board for SO package.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP97 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
OP97
DIE CHARACTERISTICS
4
3
2
1
1.
2.
3.
4.
5.
6.
7.
8.
OUTPUT
+VS
OFFSET NULL
OFFSET NULL
–INPUT
+INPUT
–VS
OVER COMP
5
6
7
8
DIE SIZE 0.063 0.074 INCH, 4,662 SQ. mils
(1.60 1.88 mm, 3.01 SQ. mm)
WAFER TEST LIMITS
(@ V =
S
15 V, V
CM
= 0 V, T
A
= 25 C, unless otherwise noted.)
Condition
Limit
250
150
±
150
120
110
110
±
13.5
±
13
0.1
600
Unit
µV
Max
pA Max
pA Max
V/mV Min
dB Min
dB Min
V Min
V Min
V/µs Min
µA
Max
Parameter
Input Offset Voltage
Input Offset Current
Input Bias Current
Large Signal Voltage Gain
Common-Mode Rejection
Power Supply Rejection
Input Voltage Range
Output Voltage Swing
Slew Rate
Supply Current
NOTES
1
Guaranteed by CMR test.
Symbol
V
OS
I
OS
I
B
A
VO
CMR
PSR
IVR
V
O
SR
I
SY
V
OUT
=
±
10 V, R
L
= 2 kΩ
V
CM
=
±
13.5
V
S
=
±
2 V to
±
20 V
(Note 1)
R
L
= 10 kΩ
No Load
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
