SRV05-4MR6
Transient Voltage
Suppressors
ESD Protection Diodes with Low
Clamping Voltage
The SRV05−4MR6 transient voltage suppressor is designed to
protect high speed data lines from ESD, EFT, and lighting.
Features
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•
•
•
•
•
Protects 4 I/O Lines
Low Working Voltage: 5 V
Low Clamping Voltage
Low Capacitance (<5 pF) for High Speed Interfaces
Transient Protection for High Speed Lines to:
IEC61000−4−2 (ESD)
±15
kV (air),
±8
kV (contact)
IEC61000−4−4 (EFT) 40 A
IEC61000−4−5 (Lightning) 12 A
•
TSOP−6 is Footprint Compatible with SOT−23 6 Lead,
SC−59 6 Lead and SC−74
•
UL Flammability Rating of 94 V−0
•
This is a Pb−Free Device
Typical Applications
LOW CAPACITANCE
TVS ARRAY
300 WATTS PEAK POWER
6 VOLTS
PIN CONFIGURATION
AND SCHEMATIC
I/O 1
V
N
2
I/O 3
6 I/O
5 V
P
4 I/O
6
1
TSOP−6
CASE 318G
PLASTIC
•
•
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•
High Speed Communication Line Protection
USB 1.1 and 2.0 Power and Data Line Protection
Digital Video Interface (DVI)
Monitors and Flat Panel Displays
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Peak Power Dissipation
8 x 20
ms
@ T
A
= 25°C (Note 1)
Operating Junction Temperature Range
Storage Temperature Range
Lead Solder Temperature
−
Maximum (10 Seconds)
Human Body Model (HBM)
Machine Model (MM)
IEC 61000−4−2 Air (ESD)
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−4 (5/50 ns)
IEC 61000−4−5 (8 x 20
ms)
Symbol
P
pk
T
J
T
stg
T
L
ESD
Value
300
−55
to +125
−55
to +150
260
16000
400
15000
8000
40
12
Unit
W
MARKING DIAGRAM
63
°C
°C
°C
V
G
G
63 = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary
depending upon manufacturing location.
M
EFT
−
A
A
ORDERING INFORMATION
Device
SRV05−4MR6T1G
Package
Shipping
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Non−repetitive current pulse per Figure 5 (Pin 5 to Pin 2)
TSOP−6 3000/Tape & Reel
(Pb−Free)
See Application Note AND8308/D for further description of
survivability specs.
©
Semiconductor Components Industries, LLC, 2009
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
SRV05−4MR6/D
November, 2009
−
Rev. 0
1
SRV05−4MR6
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
I
PP
V
C
V
RWM
I
R
V
BR
I
T
I
F
V
F
P
pk
C
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
PP
Working Peak Reverse Voltage
Maximum Reverse Leakage Current @ V
RWM
Breakdown Voltage @ I
T
Test Current
Forward Current
Forward Voltage @ I
F
Peak Power Dissipation
Capacitance @ V
R
= 0 and f = 1.0 MHz
I
PP
V
C
V
BR
V
RWM
I
R
V
F
I
T
V
I
F
I
Uni−Directional TVS
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS
(T
J
=25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Reverse Leakage Current
Clamping Voltage
Clamping Voltage
Junction Capacitance
Junction Capacitance
Clamping Voltage
Symbol
V
RWM
V
BR
I
R
V
C
V
C
C
J
C
J
V
C
(Note 2)
I
T
=1 mA, (Note 3)
V
RWM
= 5 V
I
PP
= 1 A (Note 4)
I
PP
= 5 A (Note 4)
V
R
= 0 V, f=1 MHz between I/O Pins and GND
V
R
= 0 V, f=1 MHz between I/O Pins
Per IEC 61000−4−2 (Note 5)
3.0
1.5
Figure 1 and 2
6.0
5.0
12.5
17.5
5.0
3.0
Conditions
Min
Typ
Max
5.0
Unit
V
V
mA
V
V
pF
pF
V
2. TVS devices are normally selected according to the working peak reverse voltage (V
RWM
), which should be equal or greater than the DC
or continuous peak operating voltage level.
3. V
BR
is measured at pulse test current I
T
.
4. Non−repetitive current pulse per Figure 5 (Any I/O Pin to Ground)
5. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
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2
SRV05−4MR6
IEC 61000−4−2 Spec.
Test
Voltage
(kV)
2
4
6
8
First Peak
Current
(A)
7.5
15
22.5
30
Current at
30 ns (A)
4
8
12
16
Current at
60 ns (A)
2
4
6
8
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
I @ 30 ns
IEC61000−4−2 Waveform
I
peak
100%
90%
Level
1
2
3
4
Figure 3. IEC61000−4−2 Spec
ESD Gun
TVS
Oscilloscope
50
W
Cable
50
W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D
−
Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
% OF PEAK PULSE CURRENT
90
80
70
60
50
40
30
20
10
0
0
20
t
P
t
r
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
PEAK VALUE I
RSM
@ 8
ms
PULSE WIDTH (t
P
) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8
ms
HALF VALUE I
RSM
/2 @ 20
ms
40
t, TIME (ms)
60
80
Figure 5. 8 X 20
ms
Pulse Waveform
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3
SRV05−4MR6
TYPICAL PERFORMANCE CURVES
(T
J
= 25°C unless otherwise noted)
5.0
JUNCTION CAPACITANCE (pF)
4.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
1
2
3
4
5
I/O lines
I/O−Ground
CLAMPING VOLTAGE (V)
4.0
30
25
20
15
10
5
0
0
2
4
6
8
10
12
V
BR
, REVERSE VOLTAGE (V)
PEAK PULSE CURRENT (A)
Figure 6. Junction Capacitance vs Reverse Voltage
Figure 7. Clamping Voltage vs. Peak Pulse Current
(8 x 20
ms
Waveform)
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SRV05−4MR6
APPLICATIONS INFORMATION
The new SRV05−4MR6 is a low capacitance TVS diode
array designed to protect sensitive electronics such as
communications systems, computers, and computer
peripherals against damage due to ESD events or transient
overvoltage conditions. Because of its low capacitance, it
can be used in high speed I/O data lines. The integrated
design of the SRV05−4MR6 offers surge rated, low
capacitance steering diodes and a TVS diode integrated in a
single package (TSOP−6). If a transient condition occurs,
the steering diodes will drive the transient to the positive rail
of the power supply or to ground. The TVS device protects
the power line against overvoltage conditions to avoid
damage to the power supply and any downstream
components.
SRV05−4MR6 Configuration Options
The SRV05−4MR6 is able to protect up to four data lines
against transient overvoltage conditions by driving them to
a fixed reference point for clamping purposes. The steering
diodes will be forward biased whenever the voltage on the
protected line exceeds the reference voltage (Vf or V
CC
+
Vf). The diodes will force the transient current to bypass the
sensitive circuit.
Data lines are connected at pins 1, 3, 4 and 6. The negative
reference is connected at pin 2. These pins must be
connected directly to ground by using a ground plane to
minimize the PCB’s ground inductance. It is very important
to reduce the PCB trace lengths as much as possible to
minimize parasitic inductances.
Option 1
Protection of four data lines and the power supply using
V
CC
as reference.
I/O 1
I/O 2
1
2
3
I/O 3
I/O 4
6
5
4
V
CC
I/O 3
I/O 4
Option 2
Protection of four data lines with bias and power supply
isolation resistor.
I/O 1
I/O 2
V
CC
1
2
3
I/O 3
I/O 4
6
5
4
10 k
The SRV05−4MR6 can be isolated from the power supply
by connecting a series resistor between pin 5 and V
CC
. A
10 kW resistor is recommended for this application. This
will maintain a bias on the internal TVS and steering diodes,
reducing their capacitance.
Option 3
Protection of four data lines using the internal TVS diode
as reference.
I/O 1
I/O 2
1
2
3
6
5
4
NC
In applications lacking a positive supply reference or
those cases in which a fully isolated power supply is
required, the internal TVS can be used as the reference. For
these applications, pin 5 is not connected. In this
configuration, the steering diodes will conduct whenever the
voltage on the protected line exceeds the working voltage of
the TVS plus one diode drop (Vc = Vf + V
TVS
).
ESD Protection of Power Supply Lines
When using diodes for data line protection, referencing to
a supply rail provides advantages. Biasing the diodes
reduces their capacitance and minimizes signal distortion.
Implementing this topology with discrete devices does have
disadvantages. This configuration is shown below:
For this configuration, connect pin 5 directly to the
positive supply rail (V
CC
), the data lines are referenced to
the supply voltage. The internal TVS diode prevents
overvoltage on the supply rail. Biasing of the steering diodes
reduces their capacitance.
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