UTOPIA.I.O
4-PORT (128 X 9 X 4)
MULTIPLEXER-.I.O
.eatures
x
x
x
x
1,6%%! #
x
x
x
x
Four Independent Input 128 x9 FIFO Queues
Nine bit wide input FIFOs
Single selectable 9 or 18 bit output bus
"UtopiaRx" or "UtopiaTx" Utopia compliant interface signaling
options
Separate clocks for input and output
Selectable Automatic byte insertion for 8-bit Receive Utopia to 16-
bit Receive Utopia compliance
Four 155Mbs ATM input channels can be consolidated into a
single 622Mbs channel with no additional glue logic
Maximum through put per device over 1.4Gbps
x
x
x
x
x
x
x
In a building block configuration multiple input channels can
be multiplexed onto a 32, 64 or 128 bit bus.
User programmable:
– byte insert/delete, UtopiaTx/UtopiaRx mode, master/slave
configuration, byte swapping
Selectable Round Robin Sequencer output control
Data clock rates to 80 MHz; access times 8.5 ns
100-pin TQPF package
Separate cell ready signals for each FIFO and cell ready
composite signal
End of cell transfer flag
.unctional Block Diagram
CRn
CRC
ECT
CSS
RTS
BDI
CELL SIZE/CELL READY
OE
RST
WCLK
ROUND
ROBIN
SEQUENCER
MSE
RRE
RCLK
MUX1
MUX2
LDM
X 18
SWP
FIFO CONTROLLER
128 BYTES
FIFO
ENR
a
CLAVR a
SOCR a
Data a (0 - 8)
ENR
b
CLAVR b
SOCR b
Data b (0 - 8)
ENR
c
CLAVR c
SOCR c
Data c (0 - 8)
ENR
d
CLAVR d
SOCR d
Data d (0 - 8)
FIFO CONTROLLER
128 BYTES
FIFO
XOE
ENS
CLAVS
SOCS
,
FIFO CONTROLLER
128 BYTES
FIFO
Q
0
- Q
8
Q
9
- Q
17
FIFO CONTROLLER
128 BYTES
FIFO
BSS
3206 drw 01
MARCH 2001
1
©2001 Integrated Device Technology, Inc.
DSC-3206/3
IDT77305
UtopiaFIFO™ 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Preliminary
Commercial and Industrial Temperature Ranges
General Description
The IDT77305 UtopiaFIFO is a high-speed, low power, four to one,
muxed FIFO with multiple programmable modes of operation. The
IDT77305 can be used as a stand alone device or as a building block
element. Within the UtopiaFIFO, the input FIFOs act as intermediate
queues for the input streams to allow synchronization with a common output
stream (see Functional Block Diagram). Each of the four input synchro-
nous (clocked) FIFOs are 64 words (128 bytes) in depth. Separate input
and output clocks are supported to 80 MHz. As a stand alone element four
independent 9-bit input streams are concentrated onto one selectable 9
or 18-bit output bus. The Bus Size Select pin (BSS) determines the
desired output bus width. In a building block configuration, multiple
devices can be used to multiplex larger numbers of input streams
onto output buses greater than 18 bits. The principle application is
in ATM networking based systems, but can be used in any data or
telecommunications application requiring the merging of indepen-
dent data streams into a single output.
FIFO selection for data output can be made internally via a round robin
which sequentially selects one of the four FIFOs. Alternatively, external
Pin Configuration
CLAVR d
ENR
d
RST
WCLK
BDI
Vcc
RTS
BSS
OE
Cr
0
CR
1
CR
2
CR
3
GND
CSS
ECT
CRC
MSE
RRE
LDM
MUX
2
MUX
1
RCLK
SWP
XOE
SOCR d
Data d 8
GND
Data d 7
Data d 6
Data d 5
Data d 4
Data d 3
Data d 2
Data d 1
Data d 0
ENR
c
CLAVR c
SOCR c
Data c 8
Data c 7
Data c 6
Data c 5
Data c 4
Vcc
Data c 3
Data c 2
Data c 1
Data c 0
ENR
b
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
100 PIN
TQFP
PN-100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CLAVS
ENS
SOCS
Vcc
Q
17
Q
16
Q
15
Q
14
GND
Q
13
Q
12
Q
11
Q
10
Q
9
Vcc
Q
8
Q
7
Q
6
Q
5
GND
Q
4
Q
3
Q
2
Q
1
Q
0
,
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
3206 drw 02
CLAVR b
SOCR b
Data b 8
Data b 7
GND
Data b 6
Data b 5
Data b 4
Data b 3
Data b 2
Data b 1
Data b 0
ENR
a
CLAVR a
SOCR a
Data a 8
Data a 7
Data a 6
Data a 5
Data a 4
Data a 3
Data a 2
Data a 1
Data a 0
Vcc
2
IDT77305
UtopiaFIFO™ 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Commercial and Industrial Temperature Ranges
Pin Description
Name
BDI
BSS
CLAVR a
CLAVR b
CLAVR c
I/O
I
I
I/O
I/O
I/O
Description
Byte Deletion/Insertion. BDI = "1" insert byte 6 or delete byte 5, BDI = "0" no change to bytes 5 or 6 (see Table 4).
Bus Size Selection. BSS = "0" 18-bit output bus, BSS = "1" 9-bit output bus.
Cell Available (FIFO-a)—Receive side. Rx mode: CLAVR notifies UtopiaFIFO an entire cell is available for transfer. It is
an input signal. Tx mode: CLAVR notifies sending agent the UtopiaFIFO can accept an entire cell. It is an output signal.
Cell Available (FIFO-b)—Receive side. Rx mode: CLAVR notifies UtopiaFIFO an entire cell is available for transfer. It is
an input signal. Tx mode: CLAVR notifies sending agent the UtopiaFIFO can accept an entire cell. It is an output signal.
Cell Available (FIFO-c)—Receive side. Rx mode: CLAVR notifies UtopiaFIFO an entire cell is available for transfer.
It is an input signal. Tx mode: CLAVR notifies sending agent the UtopiaFIFO can accept an entire cell. It is an
output signal.
Cell Available (FIFO-d)—Receive side. Rx mode: CLAVR notifies UtopiaFIFO an entire cell is available for transfer.
It is an input signal. Tx mode: CLAVR notifies sending agent the UtopiaFIFO can accept an entire cell. It is an
output signal.
Cell Available (sender side). Notifies controlling agent a cell is available.
Cell Ready, FIFO-n. For
OE
LOW and
RST
HIGH, CR-n is an output (HIGH if FIFO-n has a cell available, LOW if
no cell available). For
RST
and
OE
both HIGH, CR-n are tri-stated. For
RST
LOW and
OE
HIGH, CRn are inputs.
See Table 1.
Cell Ready Composite. For
OE
LOW and
RST
HIGH, CRC is an output (HIGH if any FIFO has cell available). For
RST
and
OE
both HIGH, CRC is tri-stated. For
RST
LOW AND
OE
HIGH, CRC is a cell size selection input [MSB].
Cell Size selection for (MSB-2).
9-bit data bus inputs for FIFO-a.
9-bit data bus inputs for FIFO-b.
9-bit data bus inputs for FIFO-c.
9-bit data bus inputs for FIFO-d.
End Cell Transfer. For
OE
LOW and
RST
HIGH, ECT is an output asserted one cycle before end of current cell
transfer. ECT goes LOW upon cell transfer completion. For
RST
and
OE
both HIGH, ECT is tri-stated. For
RST
LOW
and
OE
HIGH, ECT is a cell size selection input [MSB-1].
Enable (FIFO-a)—Receive Side. Rx mode:
ENR
is an output initiating data transfer to the receiver (input) side.
Tx mode:
ENR
is an input initiating data transfer to the receiver side.
Enable (FIFO-b)—Receive Side. Rx mode:
ENR
is an output initiating data transfer to the receiver (input) side.
Tx mode:
ENR
is an input initiating data transfer to the receiver side.
Enable (FIFO-c)—Receive Side. Rx mode:
ENR
is an output initiating data transfer to the receiver (input) side.
Tx mode:
ENR
is an input initiating data transfer to the receiver side.
Enable (FIFO-d)—Receive Side. Rx mode:
ENR
is an output initiating data transfer to the receiver (input) side.
Tx mode:
ENR
is an input initiating data transfer to the receiver side.
Enable (sender side). Enables current word transfer. Rx mode: an input to UtopiaFIFO. Tx mode: an output to
receiving system.
Logic and supply ground.
3206 tbl 01
CLAVR d
I/O
CLAVS
CR0 - CR3
I/O
I/O
CRC
CSS
DATA a
DATA b
DATA c
DATA d
ECT
I/O
I/O
I
I
I
I
I/O
ENR
a
ENR
b
ENR
c
ENR
d
ENS
GND
I/O
I/O
I/O
I/O
I/O
____
3
IDT77305
UtopiaFIFO™ 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Preliminary
Commercial and Industrial Temperature Ranges
Pin Description (con't.)
Name
LDM
MSE
MUX1
MUX2
I/O
I/O
I
I/O
I/O
I
O
I
I
I
I
I
I
I
I
O
I
Description
Load Mux. RRE = "1" and MSE = "1": LDM is an output telling Slave to latch the Mux select address on the next
clock cycle, RRE = "0" and MSE = "1": LDM is an input that latches the Mux address for the next cell transfer.
Master/Slave Enable. MSE = "1" master mode, MSE = "0" slave mode.
MUX1 address. With RRE = "1": MUX1 outputs FIFO address LSB: with RRE = "0": MUX1 is input address LSB of
selected FIFO.
MUX2 address. With RRE = "1": MUX2 outputs FIFO address MSB: with RRE = "0": MUX2 is input addre MSB of
selected FIFO.
Output Enable. In combination with RST, it sets CR0-3 as either output cell available signals, input cell size values or
tri-state outputs (see Table 1).
Data bus output.
Data read clock.
Round Robin Enable. RRE = "1" round robin sequencer enabled. RRE = "0" sets mux select lines and LDM as
inputs to provide user control over selected FIFO.
Reset. Clears all FIFO memory locations, read/write pointers, RR sequencer.
Receive/Transmit mode Selection RTS = "0" Utopia Rx mode, RTS = "1" UtopiaTx mode.
Start Of Cell (FIFO-a)—Receive side. Active on first byte when CLAVR and
ENR
are asserted. After first byte read,
SOCR is ignored until full cell has been received.
Start Of Cell (FIFO-b)—Receive side. Active on first byte when CLAVR and
ENR
are asserted. After first byte read,
SOCR is ignored until full cell has been received.
Start Of Cell (FIFO-c)—Receive side. Active on first byte when CLAVR and
ENR
are asserted. After first byte read,
SOCR is ignored until full cell has been received.
Start Of Cell (FIFO-d)—Receive side. Active on first byte when CLAVR and
ENR
are asserted. After first byte read,
SOCR is ignored until full cell has been received.
Start of Cell (sender side). Assertion: first word is currently on output bus.
Swap Enable. Swaps high byte and low byte of current word. SWP = "0": First word is placed in lower byte (Q0-Q7)
of 16-bit output (little endian), SWP = "1": first word is placed in upper byte (Q9-Q16) of 16-bit output (big endian
Utopia compliant cell format).
Logic and supply V
CC
.
Data write clock.
Data bus output enable.
3206 tbl 02
OE
Qn
RCLK
RRE
RST
RTS
SOCR a
SOCR b
SOCR c
SOCR d
SOCS
SWP
V
CC
WCLK
____
I
I
XOE
4
IDT77305
UtopiaFIFO™ 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
Symbol
V
TERM
T
A
T-Bias
T-STG
I
OUT
Terminal Voltage with respect to ground
Operating Temperature
Temperature under Bias
Storage Temperature
DC Output Current
Rating
Commercial
-0.5 to +7.0
0 to +70
-55 to +155
-55 to +155
50
Industrial
-0.5 to +7.0
-40 to +85
-55 to +155
-55 to +155
50
Unit
V
C
C
C
mA
3206 tbl 03
Recommended DC Operating Conditions
Symbol
V
CC
GND
V
IH
V
IL
Commercial Supply Voltage
Supply Voltage
Input High Voltage Commercial
Input Low Voltage Commercial
Parameter
Min.
4.5
0
2.0
-0.3
Typ.
5.0
0
____
Max.
5.5
0
V
CC
+0.3
0.8
Unit
V
V
V
V
3206 tbl 04
____
DC Electrical Characteristics
Symbol
I
LI
I
LO
V
OH
V
OL
I
CC1
Input Leakage Current
Output Leakage Current
Output Logic "1" Voltage, I
OH
=-4mA@2.4V
Output Logic "0" Voltage I
OL
=+4mA@0.4V
Active Power Supply Current
Parameter
Min.
-1
-10
2.4
____
Typ.
____
Max.
1
10
____
Unit
µA
µA
V
V
mA
3206 tbl 05
____
____
____
0.4
150
____
____
Capacitance
Symbol
C
IN
C
OUT
Input Capacitance
Output Capacitance
Parameter
Conditions
V
IN
=0V
V
OUT
=0V
Max.
10
10
Unit
pF
pF
3206 tbl 06
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
