A Clock Enable (CEN) pin allows operation of the IDT71V65602/5802
to be suspended as long as necessary. All synchronous inputs are
the need to control
OE
x
Single R/W (READ/WRITE) control pin
ignored when (CEN) is high and the internal device registers will hold their
W
x
Positive clock-edge triggered address, data, and control
previous values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the
signal registers for fully pipelined applications
x
4-word burst capability (interleaved or linear)
user to deselect the device when desired. If any one of these three are
x
Individual byte write (BW
1
-
not asserted when ADV/LD is low, no new memory operation can be
BW BW
4
) control (May tie active)
x
Three chip enables for simple depth expansion
initiated. However, any pending data transfers (reads or writes) will be
x
completed. The data bus will tri-state two cycles after chip is deselected or
3.3V power supply (±5%)
x
2.5V I/O Supply (V
DDQ
)
a write is initiated.
x
Power down controlled by ZZ input
The IDT71V65602/5802 have an on-chip burst counter. In the burst
x
Packaged in a JEDEC standard 100-lead plastic thin quad
mode, the IDT71V65602/5802 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the
LBO
input pin. The
LBO
pin selects between linear and
Description
The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit interleaved burst sequence. The ADV/LD signal is used to load a new
(9 Megabit) synchronous SRAMs. They are designed to eliminate dead external address (ADV/LD = LOW) or increment the internal burst counter
bus cycles when turning the bus around between reads and writes, or (ADV/LD = HIGH).
The IDT71V65602/5802 SRAM utilize IDT's latest high-performance
writes and reads. Thus, they have been given the name ZBT
TM
, or Zero
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100-
Bus Turnaround.
lead thin plastic quad flatpack (TQFP) as well as a 119-lead ball grid array (BGA).
Pin Description Summary
A
0
-A
1 8
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
A DV /LD
LBO
TM S
TDI
TCK
TDO
ZZ
I/O
0
-I/O
3 1
, I/O
P 1
-I/O
P 4
V
DD
, V
DDQ
V
SS
A d d re s s Inp uts
Chip E nab le s
O utp ut E nab le
Re ad /W rite S ig nal
Clo c k E nab le
Ind ivid ual B y te W rite S e le cts
Clo ck
A d v anc e b urst ad d re s s / Lo ad ne w ad d re ss
Line ar / Inte rle av e d B urs t O rd e r
Te st M o d e S e le c t
Te st Data Inp ut
Te st Clo ck
Te st Data O utp ut
S le e p M o d e
Data Inp ut / O utp ut
Co re P o we r, I/O P o we r
G ro und
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
O utp ut
Inp ut
I/O
S up p ly
S up p ly
S y nchro no us
S y nchro no us
A s ync hro no us
S y nchro no us
S y nchro no us
S y nchro no us
N/A
S y nchro no us
S tatic
N/A
N/A
N/A
N/A
A s ync hro no us
S y nchro no us
S tatic
S tatic
5303 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
