3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
1,024 x 1,024
.EATURES:
•
•
IDT72V70210
32 serial input and output streams
1,024 x 1,024 channel non-blocking switching at 2.048 Mb/s
•
Per-channel Variable Delay Mode for low-latency applications
•
Per-channel Constant Delay Mode for frame integrity applications
•
Automatic identification of ST-BUS
®
and GCI serial streams
•
Automatic frame offset delay measurement
•
Per-stream frame delay offset programming
•
Per-channel high impedance output control
•
Per-channel processor mode to allow microprocessor writes to
TX streams
•
Direct microprocessor access to all internal memories
•
Memory block programming for quick set-up
•
IEEE-1149.1 (JTAG) Test Port
•
Internal Loopback for testing
•
·
Available in 144-pin Ball Grid Array (BGA) and 144-pin Thin Quad
•
•
Flatpack (TQFP) packages
Operating Temperature Range -40°C to +85°C
°
°
3.3V I/O with 5V tolerant inputs and TTL compatible outputs
DESCRIPTION:
The IDT72V70210 has a non-blocking switch capacity of 1,024 x 1,024
channels at 2.048 Mb/s. With 32 inputs and 32 outputs, programmable per
stream control, and a variety of operating modes the IDT72V70210 is designed
for the TDM time slot interchange function in either voice or data applications.
Some of the main features of the IDT72V70210 are low power 3.3 Volt
operation, automatic ST-BUS
®
/GCI sensing, memory block programming,
simple microprocessor interface, one cycle direct internal memory accesses,
JTAG Test Access Port (TAP) and per stream programmable input offset delay,
variable or constant throughput modes, internal loopback, output enable, and
Processor Mode.
.UNCTIONAL BLOCK DIAGRAM
Vcc GND
RESET
TMS
TDI
TDO
TCK
TRST
ODE
Test Port
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
RX16
RX17
RX18
RX19
RX20
RX21
RX22
RX23
RX24
RX25
RX26
RX27
RX28
RX29
RX30
RX31
Loopback
Output
MUX
Data Memory
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
Internal
Registers
Connection
Memory
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
TX8
TX9
TX10
TX11
TX12
TX13
TX14
TX15
TX16
TX17
TX18
TX19
TX20
TX21
TX22
TX23
TX24
TX25
TX26
TX27
TX28
TX29
TX30
TX31
Timing Unit
Microprocessor Interface
5714 drw01
CLK
F0i
FE
IC
DS
CS
R/W
A0-A11
DTA
D0-D15
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS
is a trademark of Mitel Corp.
JANUARY 2002
DSC-5714/3
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
SYMBOL
GND
V
CC
TX0-31
RX0-31
F0i
FE
CLK
TMS
TDI
TDO
TCK
TRST
NAME
Ground.
V
CC
TX Output 0 to 31
(Three-state Outputs)
RX Input 0 to 31
Frame Pulse
Frame Evaluation
Clock
Test Mode Select
Test Serial Data In
Test Serial Data Out
Test Clock
Test Reset
I/O
DESCRIPTION
Ground Rail.
+3.3 Volt Power Supply.
O Serial data output stream. These streams have a data rate of 2.048 Mb/s.
Serial data input stream. These streams have a data rate of 2.048 Mb/s.
This input accepts and automatically identifies frame synchronization signals formatted according to
ST-BUS
®
and GCI specifications.
I This pin is the frame measurement input.
I Serial clock for shifting data in/out on the serial streams (RX/TX 0-31). This input accepts a 4.096 MHz clock.
I JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal
pull-up when not driven.
I JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
O JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when
JTAG scan is not enabled.
I Provides the clock to the JTAG test logic.
I Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled
by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure
that the IDT72V70210 is in the normal functional mode.
I This input (active LOW) puts the IDT72V70210 in its reset state that clears the device internal counters,
registers and brings TX0-31 and microport data outputs to a high-impedance state. The time constant for a
power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation,
the
RESET
pin must be held LOW for a minimum of 100ns to reset the device.
I This active LOW input works in conjunction with
CS
to enable the read and write operations.
I This input controls the direction of the data bus lines during a microprocessor access.
I Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70210.
I These pins allow direct access to Connection Memory, Data Memory and internal control registers.
I/O These pins are the data bits of the microprocessor port.
O This active LOW signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives
HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up
resistor is required to hold a HIGH level when the pin is in high-impedance.
I This is the output enable control for the TX0-31 serial outputs. When ODE input is LOW and the OSB bit of
the CR register is LOW, TX0-31 are in a high-impedance state. If this input is HIGH, the TX0-31 output
drivers are enabled. However, each channel may still be put into a high-impedance state by using the per
channel control bit in the connection memory.
I
I
RESET
Device Reset
(Schmitt Trigger Input)
DS
R/W
CS
A0-11
D0-15
DTA
Data Strobe
Read/Write
Chip Select
Address Bus 0 to 11
Data Bus 0-15
Data Transfer
Acknowledgment
Output Drive Enable
ODE
4
IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED):
The IDT72V70210 is capable of switching up to 1,024 x 1,024 channels
without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
device maintains frame integrity in data applications and minimizes throughput
delay for voice applications on a per channel basis.
The 32 serial input streams (RX) of the IDT72V70210 can be run 2.048 Mb/s
allowing 32 channels per 125µs frame. The data rates on the output streams
(TX) are identical to those on the input stream.
With two main operating modes, Processor Mode and Connection Mode,
the IDT72V70210 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor (Connection Memory). As
control and status information is critical in data transmission, the Processor Mode
is especially useful when there are multiple devices sharing the input and output
streams.
With data coming from multiple sources and through different paths, data
entering the device is often delayed. To handle this problem, the IDT72V70210
has a frame evaluation feature to allow individual streams to be offset from the
frame pulse in half clock-cycle intervals up to +4.5 clock cycles.
The IDT72V70210 also provides a JTAG test access port, an internal
loopback feature, memory block programming, a simple microprocessor
interface and automatic ST-BUS
®
/GCI sensing to shorten setup time, aid in
debugging and ease use of the device without sacrificing capabilities.
The IDT72V70210 provides two different interface timing modes, ST-BUS
®
or GCI. The IDT72V70210 automatically detects the presence of an input frame
pulse and identifies it as either ST-BUS
®
or GCI. In ST-BUS
®
format, every
second falling edge of the master clock marks a bit boundary and the data is
clocked in on the rising edge of CLK, three quarters of the way into the bit cell.
In GCI format, every second rising edge of the master clock marks the bit
boundary and data is clocked in on the falling edge of CLK at three quarters of
the way into the bit cell.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual
input streams to be offset with respect to the output stream channel
alignment (i.e.
F0i).
Although all input data comes in at the same speed, delays
can be caused by variable path serial backplanes and variable path lengths
which may be implemented in large centralized and distributed switching
systems. Because data is often delayed this feature is useful in compensating
for the skew between clocks.
Each input stream can have its own delay offset value by programming the
frame input offset registers (FOR, Table 8). The maximum allowable skew is +4
master clock (CLK) periods forward with a resolution of 1/2 clock period. The
output frame offset cannot be offset or adjusted.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V70210 provides the frame evaluation (FE) input to deter-
mine different data input delays with respect to the frame pulse
F0i.
A measurement cycle is started by setting the start frame evaluation (SFE)
bit low for at least one frame. When the SFE bit in the Control Register is changed
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
to 11 of the FAR register. The SFE bit must be set to zero before a new
measurement cycle is started.
In ST-BUS
®
mode, the falling edge of the frame measurement signal (FE)
is evaluated against the falling edge of the ST-BUS
®
frame pulse. In GCI mode,
the rising edge of FE is evaluated against the rising edge of the GCI frame pulse.
See Table 7 and Figure 1 for the description of the frame alignment register.
MEMORY BLOCK PROGRAMMING
The IDT72V70210 provides users with the capability of initializing the entire
connection memory block in two frames. To set bits 12 to 15 of every connection
memory location, first program the desired pattern in bits 5 to 8 of the Control
Register.
The block programming mode is enabled by setting the memory block
program (MBP) bit of the control register high. When the block programming
enable (BPE) bit of the Control Register is set to high, the block programming
data will be loaded into the bits 12 to 15 of every connection memory location.
The other connection memory bits (bit 0 to bit 11) are loaded with zeros. When
the memory block programming is complete, the device resets the BPE bit to zero.
LOOPBACK CONTROL
The loopback control (LPBK) bit of each connection memory location allows
the TX output data to be looped backed internally to the RX input for diagnostic
purposes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., data from TXn channel m routes to
the RXn channel m internally); if the LPBK bit is low, the loopback feature is
.UNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY
All data that comes in through the RX inputs go through a serial-to-
parallel conversion before being stored into internal Data Memory. The 8 KHz
frame pulse (F0i) is used to mark the 125µs frame boundaries and to sequentially
address the input channels in Data Memory.
Data output on the TX streams may come from either the Serial Input Streams,
RX0-31, (Data Memory) or from the microprocessor (Connection Memory). In
the case that RX input data is to be output, the addresses in connection memory
are used to specify a stream and channel of the input. The connection memory
is setup in such a way that each location corresponds to an output channel for
each particular stream. In that way, more than one channel can output the same
data.
In Processor Mode, the microprocessor writes data to the connection
memory locations corresponding to the stream and channel that is to be
output. The lower half (8 least significant bits) of the connection memory
is output every frame until the microprocessor changes the data or mode
of the channel. By using this Processor Mode capability, the microproces-
sor can access input and output time-slots on a per channel basis.
The four most significant bits of the connection memory are used to control
per channel functions of the out put streams. Specifically, there are bits for
Processor or Connection mode, Constant or Variable delay, enables or
disables of output drivers, and controls for the Loopback function.
If the per channel OE is set to zero, only that particular channel (8-bits) will
be in the high-impedance state. If however, the ODE input pin is low or the Output
Standby Bit (OSB) in the Control Register is low, all of the outputs will be in a
high-impedance state even if a particular channel in connection memory has
enabled the output for that channel. In other words, the ODE pin and OSB control
bit are master output enables for the device (Table 3).
SERIAL DATA INTERFACE TIMING
The master clock frequency must always be twice the data rate. For a serial
data rates of 2.048 Mb/s, the master clock (CLK) must be at 4.096 MHz. The
input and output stream data rates will always be identical.
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