Hitachi SuperH™ RISC engine
SH7729R
Hardware Manual
ADE-602-229B
Rev. 3.0
9/18/2002
Hitachi, Ltd.
Cautions
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contained in this document.
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have received the latest product standards or specifications before final design, purchase or
use.
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However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
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life support.
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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
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Preface
The SH7729R is a microprocessor that integrates peripheral functions necessary for system
configuration with a 32-bit internal architecture SH2-DSP CPU as its core.
The SH7729R's on-chip peripheral functions include a cache memory, internal X/Y memory, an
interrupt controller, timers, three serial communication interfaces, a real time clock (RTC),
memory management unit (MMU), a user break controller (UBC), a bus state controller (BSC),
and I/O ports, making it ideal for use as a microcomputer in electronic devices that require high
speed together with low power consumption.
Intended Readership: This manual is intended for users undertaking the design of an application
system using the SH7729R. Readers using this manual require a basic
knowledge of electrical circuits, logic circuits, and microcomputers.
Purpose:
The purpose of this manual is to give users an understanding of the hardware
functions and electrical characteristics of the SH7729R.Details of execution
instructions can be found in the SH-3, SH-3E, SH3-DSP Programming
Manual, which should be read in conjunction with the present manual.
Using this Manual:
•
For an overall understanding of the SH7729R's functions
Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system
control functions, peripheral functions, and electrical characteristics.
•
For a detailed understanding of CPU functions
Refer to the separate publication SH-3, SH-3E, SH3-DSP Programming Manual.
Note on bit notation: Bits are shown in high-to-low order from left to right.
Related Material:
The latest information is available at our Web Site. Please make sure that you
have the most up-to-date information available.
(http://www.hitachisemiconductor.com/)
Rev. 3.0, 09/02, page iii of xxxviii
User's Manuals on the SH7729R:
Manual Title
SH7729R Hardware Manual
SH-3, SH-3E, SH-3DSP Programming Manual
ADE No.
This manual
ADE-602-096
Users manuals for development tools:
Manual Title
C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual
Simulator Debugger User's Manual
Hitachi Embedded Workshop User's Manual
ADE No.
ADE-702-246
ADE-702-186
ADE-702-201
Rev. 3.0, 09/02, page iv of xxxviii
List of Items Revised or Added for This Version
Section
1.3.2 Pin Function
Table 1.3 SH7729R Pin
Functions
Page
10, 18
Description
Note
*6
added, and text added to
*4
4
5
6
7
D1
D3
E1
C3
XTAL2
EXTAL2
Vss-RTC
*
1
NMI
O
I
—
I
On-chip RTC crystal oscillator pin
On-chip RTC crystal oscillator
pin
*
6
RTC power supply (0 V)
Nonmaskable interrupt request
*4
Drive high when using the user system alone, and not using an
emulator or the H-UDI. When this pin is low or open,
RESETP
may be
masked (see section 23).
*5
B2, B1, C1, U1, V1, W1, V2, W2, W3, W17, W18, W19, V18, V19,
B19, A19, B18, A18, A17, A3, A2, and A1 are NC pins. No connection
should be made to these pins.
*6
If EXTAL2 is not used, pull this pin up to the Vcc-RTC level.
7.2.3 IRL Interrupts
165
Explanation added to 8th line as follows
Correct operation cannot be guaranteed if the level is not maintained.
However, the priority level can be changed to a higher one.
7.2.4 PINT Interrupts
166
Explanation added to 6th line as follows
The PINT interrupt level should be held until the interrupt is accepted and
interrupt handling is started. Correct operation cannot be guaranteed if the
level is not maintained.
7.5 Interrupt Response
Time
Table 7.8 Interrupt
Response Time
188,
189
Note
*5
deleted
0.5
×
Icyc
+ 3.5
×
Pcyc
0.5
×
Icyc
+ 1.5
×
Pcyc
*
5
0.5
×
Icyc
+ 3
×
Pcyc
*
6
Response
time
Total
(5.5 + X)
×
Icyc
+ 0.5
×
Bcyc
+ 0.5
×
Pcyc
(5.5 + X)
×
Icyc
+ 1
×
Bcyc +
4.5
×
Pcyc
*
4
(5.5 + X)
×
Icyc
+ 3.5
×
Pcyc
*
5
(5.5 + X)
×
Icyc
+ 1.5
×
Pcyc
*
5
(5.5 + X)
×
Icyc
+ 3
×
Pcyc
*
6
8.5
*
5
/11.5
*
6
10.5 + S
*
5
16.5 + S
*
6
Minimum
case
*
2
Maximum
case
*
3
7.5
8.5 + S
16.5
26.5 + S
12.5
18.5 + S
*4
IRQ mode
*5
Modules: TMU, RTC, SCI, WDT, REFC
*6
Modules: DMAC, ADC, IrDA, SCIF
Rev. 3.0, 09/02, page v of xxxviii
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