PROTECTION PRODUCTS
Description
The SFC05-5 is a five line flip chip TVS array. They are
state-of-the-art devices that utilize solid-state silicon-
avalanche technology for superior clamping perfor-
mance and DC electrical characteristics. The SFC
series TVS diodes are designed to protect sensitive
semiconductor components from damage or latch-up
due to electrostatic discharge (ESD) and other voltage
induced transient events.
The SFC05-5 is a 6-bump, 0.5mm pitch flip chip array
with a 3x2 bump grid. It measures 1.5 x 1.0 x
0.65mm. This small outline makes the SFC05-5
especially well suited for portable applications. CSP
TVS devices are compatible with current pick and place
equipment and assembly methods.
Each device will protect up to five data or I/O lines.
The flip chip design results in lower inductance, virtually
eliminating voltage overshoot due to leads and inter-
connecting bond wires. They may be used to meet the
ESD immunity requirements of IEC 61000-4-2, Level 4
(±15kV air, ±8kV contact discharge).
ChipClamp
ΤΜ
Flip Chip TVS Diode Array
PRELIMINARY
Features
200 Watts peak pulse power (tp = 8/20µs)
Transient protection for data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 20A (8/20µs)
Small chip scale package requires less board space
Low profile (< 0.65mm)
No need for underfill material
Protects five I/O or data lines
Low clamping voltage
Working voltage: 5V
Solid-state silicon-avalanche technology
SFC05-5
Mechanical Characteristics
JEDEC MO-211, 0.50 mm Pitch Flip Chip Package
Non-conductive top side coating
Marking : Marking Code
Packaging : Tape and Reel
Applications
Cell Phone Handsets and Accessories
Personal Digital Assistants (PDA’s)
Notebook and Hand Held Computers
Portable Instrumentation
Smart Cards
MP3 Players
GPS
Device Dimensions
Schematic & PIN Configuration
SFC05-5 Maximum Dimensions (mm)
3 x 2 Grid CSP TVS (Bottom View)
Revision 08/02/04
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SFC05-5
PROTECTION PRODUCTS
Absolute Maximum Rating
R ating
Peak Pulse Power (tp = 8/20µs)
Peak Pulse Current (tp = 8/20µs)
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Operating Temperature
Storage Temperature
Symbol
P
p k
I
P P
V
ESD
T
J
T
STG
Value
200
20
>25
>15
-55 to +125
-55 to +150
PRELIMINARY
Units
Watts
A
kV
°C
°C
Electrical Characteristics (T=25
o
C)
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamp ing Voltage
Clamp ing Voltage
Junction Cap acitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
C
j
Conditions
Minimum
Typical
Maximum
5
Units
V
V
I
t
= 1mA
V
RWM
= 5V, T=25°C
I
PP
= 5A, tp = 8/20µs
Any I/O to Ground
I
PP
= 20A, tp = 8/20µs
Any I/O to Ground
V
R
= 0V, f = 1MHz
6
10
9.5
11
350
µA
V
V
pF
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SFC05-5
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
Peak Pulse Power - P
pk
(kW)
PRELIMINARY
Power Derating Curve
110
100
% of Rated Power or
PP
I
90
80
70
60
50
40
30
20
10
1
0.1
0.01
0.1
1
10
Pulse Duration - tp (µs)
100
1000
0
0
25
50
75
100
o
125
150
Ambient Temperature - T
A
( C)
Pulse Waveform
110
100
90
80
Percent of I
PP
70
60
50
40
30
20
10
0
0
5
10
15
Time (µs)
20
25
30
td = I
PP
/2
e
-t
Clamping Voltage vs. Peak Pulse Current
Waveform
Parameters:
tr = 8µs
td = 20µs
10.00
9.00
Clamping Voltage - V
c
(V)
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
0
5
10
15
20
25
Peak Pulse Current - I
PP
(A)
Waveform
Parameters:
tr = 8µs
td = 20µs
ESD Clamping (8kV Contact Discharge)
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SFC05-5
PROTECTION PRODUCTS
Applications Information
Device Connection Options
The SFC05-5 has solder bumps located in a 3 x 2
matrix layout on the active side of the device. The
bumps are designated by the numbers 1 - 3 along the
horizontal axis and letters A - B along the vertical axis.
The lines to be protected are connected at bumps A1,
B1, A2, A3, and B3. Bump B2 is connected to ground.
All path lengths should be kept as short as possible to
minimize the effects of parasitic inductance in the
board traces.
Flip Chip TVS
Flip chip TVS devices are wafer level chip scale pack-
ages. They eliminate external plastic packages and
leads and thus result in a significant board space
savings. Manufacturing costs are minimized since they
do not require an intermediate level interconnect or
interposer layer for reliable operation. They are com-
patible with current pick and place equipment further
reducing manufacturing costs. Certain precautions
and design considerations have to be observed how-
ever for maximum solder joint reliability. These include
solder pad definition, board finish, and assembly
parameters.
Printed Circuit Board Mounting
Non-solder mask defined (NSMD) land patterns are
recommended for mounting the SFC05-5. Solder
mask defined (SMD) pads produce stress points near
the solder mask on the PCB side that can result in
solder joint cracking when exposed to extreme fatigue
conditions. The recommended pad size is 0.225 ±
0.010 mm with a solder mask opening of 0.350 ±
0.025 mm.
Grid Courtyard
The recommended grid placement courtyard is 1.3 x
1.8 mm. The grid courtyard is intended to encompass
the land pattern and the component body that is
centered in the land pattern. When placing parts on a
PCB, the highest recommended density is when one
courtyard touches another.
To Connector
PRELIMINARY
Device Schematic and Pin Configuration
Layout Example
To Protected IC
Ground
To Protected IC
NSMD Package Footprint
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SFC05-5
PROTECTION PRODUCTS
Applications Information
(Continued)
Printed Circuit Board Finish
A uniform board finish is critical for good assembly
yield. Two finishes that provide uniform surface coat-
ings are immersion nickel gold and organic surface
protectant (OSP). A non-uniform finish such as hot air
solder leveling (HASL) can lead to mounting problems
and should be avoided.
Stencil Design
A properly designed stencil is key to achieving ad-
equate solder volume without compromising assembly
yields. A 0.100mm thick, laser cut, electro-polished
stencil with 0.275mm square apertures and rounded
corners is recommended.
Reflow Profile
The flip chip TVS can be assembled using the reflow
requirements for IPC/JEDEC standard J-STD-020 for
assembly of small body components. During reflow,
the component will self-align itself on the pad.
Circuit Board Layout Recommendations for Suppres-
sion of ESD
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
Minimize the path length between the TVS and the
protected line.
Minimize all conductive loops including power and
ground loops.
The ESD transient return path to ground should be
kept as short as possible.
Never run critical signals near board edges.
Use ground planes whenever possible.
Assembly Guideline for Pb-Free Soldering
The following are recommendations for the assembly
of this device:
Assembly Parameter
Solder Ball Comp osition
Solder Stencil Design
Solder Stencil Thickness
Solder Paste Comp osition
Solder Paste Typ e
Solder Reflow Profile
PCB Solder Pad Design
PCB Pad Finish
R ecommendation
95.5Sn/3.8Ag/0.7Cu
Same as the SnPb design
0.100 mm (0.004")
Sn Ag (3-4) Cu (0.5-0.9)
Typ e 4 size sp here or smaller
p er JEDEC J-STD-020
Same as the SnPb Design
OSP or AuN i
PRELIMINARY
Stencil Design
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