Cypress PLD devices are high-speed electrically program-
mable logic devices. These devices utilize the sum-of-products
(AND-OR) structure providing users the ability to program
custom logic functions for unique requirements.
In an unprogrammed state the AND gates are connected via
EPROM cells to both the true and complement of every input.
By selectively programming the EPROM cells, AND gates may
be connected to either the true or complement or disconnected
from both true and complement inputs.
I
6
I
5
I
4
I
3
I
2
CP/I
1
Logic Block Diagram
V
SS
12
I
11
I
10
I
9
I
8
I
7
PROGRAMMABLE
AND ARRAY
8
8
8
OE
8
OE
8
OE
8
OE
8
OE
8
OE
8
OE
8
OE
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
13
I/OE
14
I/O
9
15
I/O
8
16
I/O
7
17
I/O
6
18
I/O
5
19
I/O
4
20
I/O
3
21
I/O
2
22
I/O
1
23
I/O
0
24
V
CC
Pin Configurations
LCC
Top View
NC
I
I
CP/I
V
CC
I/O 0
I/O 1
STD PLCC
Top View
I
I
I
CP/I
V CC
I/O0
I/O1
JEDEC PLCC
Top View
I
I
CP/I
NC
V CC
I/O0
I/O 1
4 3 2 1 2827 26
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
NC
I
I
I
NC
I
I
I
5
6
7
8
9
10
11
[1]
I
I
I
I
I
I
NC
5
6
7
8
9
10
11
4 3 2 1 282726
25
24
23
PLDC20G10 22
PLDC20G10B
21
20
19
12131415161718
V SS
I/OE
I/O9
I/O8
NC
4 3 2 1 2827 26
NC
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
NC
I
I
NC
I
I
NC
5
6
7
8
9
10
11
25
24
23
PLDC20G10
PLDC20G10B 22
21
20
121314 1516 1718 19
V
SS
I/OE
I/O 9
I/O 8
I
I
I
25
24
23
CG7C323–A
CG7C323B–A 22
21
20
121314 1516 1718 19
VSS
NC
I/OE
I/O 9
I/O 8
I
I
I/O
2
I/O
3
I/O
4
NC
I/O
5
I/O
6
I/O
7
Note:
1. The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The
difference is in the location of the “no connect” or NC pins.
Cypress Semiconductor Corporation
Document #: 38-03010 Rev. *A
I
I
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised April 20, 2004
USE ULTRA37000™ FOR
ALL NEW DESIGNS
Selection Guide
I
CC
(mA)
Generic
Part Number
20G10B–15
20G10B–20
20G10B–25
20G10–25
20G10–30
20G10–35
20G10–40
55
80
55
80
35
40
Com/Ind
70
70
100
100
25
30
30
35
Mil
t
PD
(ns)
Com/Ind
15
20
20
25
15
20
Mil
t
S
(ns)
Com/Ind
12
12
15
18
Mil
PLDC20G10B
PLDC20G10
t
CO
(ns)
Com/Ind
10
12
15
20
25
25
15
15
Mil
Functional Description
Cypress PLDC20G10 uses an advanced 0.8-micron CMOS
technology and a proven EPROM cell as the programmable
element. This technology and the inherent advantage of being
able to program and erase each cell enhances the reliability
and testability of the circuit. This reduces the burden on the
customer to test and to handle rejects.
A preload function allows the registered outputs to be preset
to any pattern during testing. Preload is important for testing
the functionality of the Cypress PLD device.
Configuration Table and in
Figures 1
through
8.
A total of eight
different configurations are possible, with the two most
common shown in
Figure 3
and
Figure 5.
The default or unpro-
grammed state is registered/active/LOW/Pin 11 OE. The
entire programmable output cell is shown in the next section.
The architecture bit ‘C1’ controls the registered/combinatorial
option. In either combinatorial or registered configuration, the
output can serve as an I/O pin, or if the output is disabled, as
an input only. Any unused inputs should be tied to ground. In
either registered or combinatorial configuration, the output of
the register is fed back to the array. This allows the creation of
control-state machines by providing the next state. The
register is clocked by the signal from Pin 1. The register is
initialized on power up to Q output LOW and Q output HIGH.
In both the combinatorial and registered configurations, the
source of the output enable signal can be individually chosen
with architecture bit ‘C2’. The OE signal may be generated
within the array, or from the external OE (Pin 13). The Pin 13
allows direct control of the outputs, hence having faster
enable/disable times.
Each output cell can be configured for output polarity. The
output can be either active HIGH or active LOW. This option is
controlled by architecture bit ‘C0’.
Along with this increase in functional density, the Cypress
PLDC20G10 provides lower-power operation through the use
of CMOS technology and increased testability with a register
preload feature.
20G10 Functional Description
The PLDC20G10 is a generic 24-pin device that can be
programmed to logic functions that include but are not limited
to: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8, 16L6, 18L4,
20L2, and 20V8. Thus, the PLDC20G10 provides significant
design, inventory and programming flexibility over dedicated
24-pin devices. It is executed in a 24-pin 300-mil molded DIP
and a 300-mil windowed cerDIP. It provides up to 22 inputs and
10 outputs. When the windowed cerDIP is exposed to UV light,
the 20G10 is erased and then can be reprogrammed.
The programmable output cell provides the capability of
defining the architecture of each output individually. Each of
the 10 output cells may be configured with registered or combi-
natorial outputs, active HIGH or active LOW outputs, and
product term or Pin 13 generated output enables. Three archi-
tecture bits determine the configurations as shown in the
Document #: 38-03010 Rev. *A
Page 2 of 14
USE ULTRA37000™ FOR
ALL NEW DESIGNS
Programmable Output Cell
OE PRODUCT TERM
OUTPUT
ENABLE
MUX
C
2
10
11
OUTPUT
SELECT
MUX
PLDC20G10B
PLDC20G10
00
D
Q
01
CP
0
INPUT/
FEED–
BACK
MUX
C
3
C
2
C
1
C
0
Q
C
1
C
0
1
PIN 13
Configuration Table
Figure
1
2
5
6
3
4
7
8
C
2
0
0
0
0
1
1
1
1
C
1
0
0
1
1
0
0
1
1
C
0
0
1
0
1
0
1
0
1
Configuration
Product Term OE/Registered/Active LOW
Product Term OE/Registered/Active HIGH
Product Term OE/Combinatorial/Active LOW
Product Term OE/Combinatorial/Active HIGH
Pin 13 OE/Registered/Active LOW
Pin 13 OE/Registered/Active HIGH
Pin 13 OE/Combinatorial/Active LOW
Pin 13 OE/Combinatorial/Active HIGH
Registered Output Configurations
C
2
= 0
C
1
= 0
C
0
= 0
CP
D
Q
D
Q
C
2
= 0
C
1
= 0
C
0
= 1
CP
Q
Q
Figure 1. Product Term OE/Active LOW
C
2
= 1
C
1
= 0
C
0
= 0
Figure 2. Product Term OE/Active HIGH
C
2
= 1
C
1
= 0
C
0
= 1
D
Q
D
Q
CP
Q
CP
Q
Figure 3. Pin 13 OE/Active LOW
Figure 4. Pin 13 OE/Active HIGH
Document #: 38-03010 Rev. *A
Page 3 of 14
USE ULTRA37000™ FOR
ALL NEW DESIGNS
Combinatorial Output Configurations
[2]
C
2
= 0
C
1
= 1
C
0
= 0
PLDC20G10B
PLDC20G10
C
2
= 0
C
1
= 1
C
0
= 1
Figure 5. Product Term OE/Active LOW
C
2
= 1
C
1
= 1
C
0
= 0
Figure 6. Product Term OE/Active HIGH
C
2
= 1
C
1
= 1
C
0
= 1
PIN 13
PIN 13
Figure 7. Pin 13 OE/Active Low
Figure 8. Pin 13 OE/Active HIGH
Note:
2. Bidirectional I/O configurations are possible only when the combinatorial output option is selected
Document #: 38-03010 Rev. *A
Page 4 of 14
USE ULTRA37000™ FOR
ALL NEW DESIGNS
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –3.0V to +7.0V
Output Current into Outputs (LOW) .............................16 mA
PLDC20G10B
PLDC20G10
DC Programming Voltage
PLDC20G10B and CG7C323B–A ............................... 13.0V
PLDC20G10 and CG7C323–A.................................... 14.0V
Latch-Up Current ..................................................... >200 mA
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