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PRODUCT PREVIEW
SMART 5 BOOT BLOCK
FLASH MEMORY FAMILY
2, 4, 8 MBIT
28F200B5, 28F400B5, 28F800B5
SmartVoltage Technology
Smart 5 Flash: 5V Reads,
5V or 12V Writes
Increased Programming Throughput
at 12V V
PP
Very High-Performance Read
2-, 4-Mbit: 60 ns Access Time
8-Mbit: 70 ns Access Time
x8/x16-Configurable Input/Output Bus
Low Power Consumption
Max 60 mA Read Current at 5V
Auto Power Savings: <1 mA Typical
Standby Current
Optimized Array Blocking Architecture
16-KB Protected Boot Block
Two 8-KB Parameter Blocks
96-KB and 128-KB Main Blocks
Top or Bottom Boot Locations
Extended Temperature Operation
–40°C to +85°C
Industry-Standard Packaging
44-Lead PSOP, 48-Lead TSOP
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Extended Block Erase Cycling
100,000 Cycles at Commercial Temp
10,000 Cycles at Extended Temp
Hardware Data Protection Feature
Absolute Hardware-Protection for
Boot Block
Write Lockout during Power
Transitions
Automated Word/Byte Program and
Block Erase
Command User Interface
Status Registers
Erase Suspend Capability
SRAM-Compatible Write Interface
Reset/Deep Power-Down Input
Provides Low-Power Mode and
Reset for Boot Operations
Pinout Compatible 2, 4, and 8 Mbit
ETOX™ Flash Technology
0.6
µ
ETOX IV Initial Production
0.4
µ
ETOX V Later Production
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Intel’s word-wide Smart 5 boot block flash memory family provides 2-, 4-, and 8-Mbit memories featuring
high-density, low-cost, nonvolatile, read/write storage solutions for a wide range of applications. Their
asymmetrically-blocked architecture, flexible voltage, and extended cycling provide highly flexible
components suitable for embedded code execution applications, such as networking infrastructure and office
automation.
Based on Intel’s boot block architecture, the word-wide Smart 5 boot block memory family enables quick and
easy upgrades for designs that demand state-of-the-art technology. This family of products comes in
industry-standard packages: the 48-lead TSOP, ideal for board-constrained applications, and the rugged,
easy to handle 44-lead PSOP.
December 1996
Order Number: 290599-003
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F200B5, 28F400B5, 28F800B5 may contain design defects or errors known are errata. Current characterized errata are
available on request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
COPYRIGHT © INTEL CORPORATION, 1996
CG-041493
E
SMART 5 BOOT BLOCK MEMORY FAMILY
CONTENTS
PAGE
PAGE
4.0 DESIGN CONSIDERATIONS........................24
4.1 Power Consumption...................................24
4.1.1 Active Power .......................................24
4.1.2 Automatic Power Savings (APS) .........24
4.1.3 Standby Power ....................................25
4.1.4 Deep Power-Down Mode.....................25
4.2 Power-Up/Down Operation.........................25
4.2.1 RP# Connected To System Reset .......25
4.3 Board Design .............................................25
4.3.1 Power Supply Decoupling....................25
4.3.2 V
PP
Trace On Printed Circuit Boards ...25
5.0 SPECIFICATIONS.........................................26
5.1 Absolute Maximum Ratings........................26
5.2 Test Conditions ..........................................26
5.3 Operating Conditions .................................27
5.4 Reset Operations .......................................27
5.6 Electrical Specifications .............................28
DC Characteristics Table ...........................28
AC Characteristics: Read Operations
Table........................................................30
AC Characteristics: Write Operations
Table........................................................32
Erase and Program Timings ......................34
APPENDIX A: Ordering Information .................35
APPENDIX B: Write State Machine: Current-
Next State Chart ..........................................36
APPENDIX C: Product Block Diagram .............37
APPENDIX D: Additional Information...............38
1.0 INTRODUCTION ............................................. 5
1.1 New Features in the Smart 5 Memory
Products ..................................................... 5
1.2 Product Overview ........................................ 5
2.0 PRODUCT DESCRIPTION.............................. 6
2.1 Pin Descriptions........................................... 6
2.2 Pinouts......................................................... 8
2.3 Memory Blocking Organization .................. 10
2.3.1 Boot Block........................................... 10
2.3.2 Parameter Blocks................................ 10
2.3.3 Main Blocks......................................... 10
3.0 PRINCIPLES OF OPERATION ..................... 13
3.1 Bus Operations .......................................... 13
3.1.1 Read ................................................... 13
3.1.2 Output Disable .................................... 14
3.1.3 Standby............................................... 14
3.1.4 Word/Byte Configuration ..................... 14
3.1.5 Deep Power-Down/Reset.................... 14
3.1.6 Write ................................................... 14
3.2 Modes of Operation ................................... 16
3.2.1 Read Array.......................................... 16
3.2.2 Read Identifier..................................... 16
3.2.3 Read Status Register .......................... 16
3.2.4 Word/Byte Program............................. 17
3.2.5 Block Erase......................................... 17
3.3 Boot Block Locking .................................... 24
3.3.1 V
PP
= V
IL
for Complete Protection ....... 24
3.3.2 WP# = V
IL
for Boot Block Locking ....... 24
3.3.3 RP# = V
HH
or WP# = V
IH
for Boot Block
Unlocking ........................................... 24
3.3.4 Note for 8-Mbit 44-PSOP Package...... 24
PRODUCT PREVIEW
3
SMART 5 BOOT BLOCK MEMORY FAMILY
E
Description
REVISION HISTORY
Number
-001
-002
Original Version
Minor changes throughout document.
Section 3.1.5 and Figure 13 redone to clarify program/erase operation abort.
Information added to Table 2, Figure 1, and Section 3.3 to clarify WP# on 8-Mbit,
44-PSOP.
Read and Write Waveforms changed to numbered format.
Typical numbers removed from DC Characteristics and Erase/Program Timings.
Minor text changes throughout document.
Figure 1, 44-PSOP pinout: mistake on pin 3 on 2-Mbit pinout corrected from A
17
to NC.
Specs t
EHQZ
and t
GHQZ
improved.
Explanations of program/erase abort commands reworked in Table 6, Command
Codes.
-003
4
PRODUCT PREVIEW
E
1.0
1.1
SMART 5 BOOT BLOCK MEMORY FAMILY
The following differences distinguish the Smart 5
boot block products from their predecessors:
•
•
A delay is required if the part is reset during an
in-progress program or erase operation.
On the fly word-byte mode switching is no
longer supported. Word-byte mode must be
configured at power-up and remain stable
during operation.
Write operations are no longer specified as
WE#- or CE#-controlled in favor of a simpler
“unified” write method, which is compatible
with either of the old methods.
INTRODUCTION
This datasheet contains specifications for 2-, 4-,
and 8-Mbit Smart 5 boot block flash memories.
Section 1 provides a feature overview. Sections 2,
3, and 4 describe the product and functionality.
Section 5 details the electrical and timing
specifications for both commercial and extended
temperature operation.
•
New Features in the
Smart 5 Memory Products
The Smart 5 boot block flash memory family offers
identical features with the BV/CV/BE/CE
SmartVoltage products, except the Smart 5 boot
block -B5 parts only support 5V V
CC
read voltage.
1.2
Product Overview
The word-wide Smart 5 boot block memory family
provides pinout-compatible flash memories at the
2-, 4- and 8-Mbit densities. The 28F200B5,
28F400B5, and 28F800B5 can be configured to
operate either in 16-bit or 8-bit bus mode, with the
data divided into individually erasable blocks.
Table 1. Smart 5 Boot Block Family: Feature Summary
Feature
V
CC
Read Voltage
V
PP
Prog/Erase Voltage
Bus-width
Speed (ns)
Commercial
Extended
Memory Arrangement
Blocking
(Top or Bottom boot
locations available)
Locking
Operating Temperature
Erase Cycling
Packages
60, 80
80
x8: 256K x 8
x16: 128K x 16
1 x 16k Boot Block
2 x 8k Parameter
1 x 96k Main Block
1 x 128k Main Block
28F200B5
28F400B5
5V
±
5%, 5V
±
10%
5V
±
10% or 12V
±
5%, auto-detected
8- or 16-bit configurable
60, 80
80
x8: 512K x 8
x16: 256K x 16
1 x 16k Boot Block
2 x 8k Parameter
1 x 96k Main Block
3 x 128k Main Block
70, 90
90
x8: 1M x 8
x16: 512K x 16
1 x 16k Boot Block Sect. 2.3,
Fig. 3-6
2 x 8k Parameter
1 x 96k Main Block
7 x 128k Main Block
Sect. 3.3
Table 10
28F800B5
Reference
Table 10
Table 10
Table 2
Table 14
Table 14
Boot Block lockable using WP# and/or RP#
All others protectable using V
PP
switch
Commercial: 0°C – +70
°C
Extended: -40°C – +85
°C
100,000 cycles at Commercial Temperature
10,000 cycles at Extended Temperature
44-PSOP, 48-TSOP
Figs. 1-2
PRODUCT PREVIEW
5
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