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SN74LVC1G58
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES415J – NOVEMBER 2002 – REVISED MARCH 2006
FEATURES
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 6.3 ns at 3.3 V
Low Power Consumption, 10-µA Max I
CC
±24-mA Output Drive at 3.3 V
I
off
Supports Partial-Power-Down Mode
Operation
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DRL PACKAGE
(TOP VIEW)
YEA, YEP, YZA,
OR YZP PACKAGE
(BOTTOM VIEW)
In1
GND
In0
1
6
In2
V
CC
Y
In1
GND
1
2
3
6
5
4
In2
V
CC
Y
In1
GND
In0
1
2
3
6
5
4
In2
V
CC
Y
In0
GND
In1
3 4
2 5
1 6
Y
V
CC
In2
2
5
4
In0
3
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This configurable multiple-function gate is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC1G58 features configurable multiple functions. The output state is determined by eight patterns of
3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XOR, inverter, and noninverter. All
inputs can be connected to V
CC
or GND.
This device functions as an independent gate, but because of Schmitt action, it may have different input
threshold levels for positive-going (V
T+
) and negative-going (V
T–
) signals.
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoStar™ – WCSP (DSBGA)
0.17-mm Small Bump – YEA
NanoFree™ – WCSP (DSBGA)
0.17-mm Small Bump – YZA (Pb-free)
–40°C to 85°C
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
SOT (SOT-563) – DRL
(1)
(2)
Tape and reel
Tape and reel
Reel of 4000
ORDERABLE PART NUMBER
SN74LVC1G58YEAR
SN74LVC1G58YZAR
Tape and reel
SN74LVC1G58YEPR
SN74LVC1G58YZPR
SN74LVC1G58DBVR
SN74LVC1G58DCKR
SN74LVC1G58DRLR
C58_
CP_
CP_
_ _ _CP_
TOP-SIDE MARKING
(2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
•
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2006, Texas Instruments Incorporated
SN74LVC1G58
CONFIGURABLE MULTIPLE-FUNCTION GATE
SCES415J – NOVEMBER 2002 – REVISED MARCH 2006
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
INPUTS
In2
L
L
L
L
H
H
H
H
In1
L
L
H
H
L
L
H
H
In0
L
H
L
H
L
H
L
H
OUTPUT
Y
L
H
L
H
H
H
L
L
LOGIC DIAGRAM (POSITIVE LOGIC)
In0
3
4
In1
1
Y
In2
6
2
Submit Documentation Feedback
www.ti.com
SN74LVC1G58
CONFIGURABLE MULTIPLE-FUNCTION GATE
SCES415J – NOVEMBER 2002 – REVISED MARCH 2006
FUNCTION SELECTION TABLE
LOGIC FUNCTION
2-input AND with inverted input
2-input NAND
2-input NAND with both inputs inverted
2-input OR
2-input OR with both inputs inverted
2-input NOR with inverted input
2-input XOR
FIGURE NO.
2, 3
1
4
4
1
2, 3
5
LOGIC CONFIGURATIONS
V
CC
A
B
A
B
Y
A
Y
1
2
3
6
5
4
Y
B
A
B
Y
A
B
Y
A
1
2
3
6
5
4
Y
B
V
CC
Figure 1. 2-Input NAND Gate
V
CC
A
B
1
A
B
2
Y
A
3
6
5
4
Y
B
A
B
A
Y
B
Figure 2. 2-Input AND Gate With Inverted A Input
V
CC
Y
1
2
Y
A
3
6
5
4
Y
B
Figure 3. 2-Input AND Gate With Inverted B Input
Figure 4. 2-Input OR Gate
V
CC
A
Y
B
A
1
2
3
6
5
4
B
Y
Figure 5. 2-Input XOR Gate
Submit Documentation Feedback
3
SN74LVC1G58
CONFIGURABLE MULTIPLE-FUNCTION GATE
SCES415J – NOVEMBER 2002 – REVISED MARCH 2006
www.ti.com
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
Supply voltage range
Input voltage range
(2)
Voltage range applied to any output in the high-impedance or power-off state
(2)
Voltage range applied to any output in the high or low
Input clamp current
Output clamp current
Continuous output current
Continuous current through V
CC
or GND
DBV package
DCK package
θ
JA
Package thermal
impedance
(4)
DRL package
YEA/YZA package
YEP/YZP package
T
stg
(1)
(2)
(3)
(4)
Storage temperature range
–65
state
(2) (3)
V
I
< 0
V
O
< 0
–0.5
–0.5
–0.5
–0.5
MAX
6.5
6.5
6.5
V
CC
+ 0.5
–50
–50
±50
±100
165
259
142
143
123
150
°C
°C/W
UNIT
V
V
V
V
mA
mA
mA
mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of V
CC
is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
(1)
MIN
V
CC
V
I
V
O
Supply voltage
Input voltage
Output voltage
V
CC
= 1.65 V
V
CC
= 2.3 V
I
OH
High-level output current
V
CC
= 3 V
V
CC
= 4.5 V
V
CC
= 1.65 V
V
CC
= 2.3 V
I
OL
Low-level output current
V
CC
= 3 V
V
CC
= 4.5 V
T
A
(1)
Operating free-air temperature
–40
Operating
Data retention only
1.65
1.5
0
0
5.5
V
CC
–4
–8
–16
–24
–32
4
8
16
24
32
85
°C
mA
mA
MAX
5.5
UNIT
V
V
V
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
4
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