MT093
8 x 12 Analog Switch Array
ISO-CMOS
Data Sheet
Features
•
•
•
•
•
•
•
•
•
Internal control latches and address decoder
Short set-up and hold times
Wide operating voltage: 4.5 V to 14.5 V
3.5Vpp analog signal capability
R
ON
65
max.
@ V
DD
=14V, 25C
R
ON
10
@ V
DD
=14V, 25C
Full CMOS switch for low distortion
Minimum feedthrough and crosstalk
Low power consumption ISO-CMOS technology
MT093AE1
MT093AP1
MT093APR1
40 Pin PDIP*
44 Pin PLCC*
44 Pin PLCC*
Tubes
Tubes
Tubes
Ordering Information
September 2011
*Pb Free Matte Tin
0C to +70C
Description
The Zarlink MT093 is fabricated in Zarlink’s ISO-
CMOS technology providing low power dissipation
and high reliability. The device contains a 8x12 array
of crosspoint switches along with a 7 to 96 line
decoder and latch circuits. Any one of the 96
switches can be addressed by selecting the
appropriate seven input bits. The selected switch can
be turned on or off by applying a logical one or zero
to the DATA input.
Applications
•
•
•
•
•
PBX systems
Mobile radio
Test equipment /instrumentation
Analog/digital multiplexers
Audio/Video switching
STROBE
DATA RESET
VDD
VSS
AX0
AX1
AX2
AX3
AY0
AY1
AY2
1
1
••••••••••••••••
7 to 96
Decoder
Latches
8 x 12
Switch
Array
96
Xi I/O
(i=0-11)
96
•••••••••••••••••••
Yi I/O (i=0-7)
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.
MT093
AX3
RESET
AY2
Y3
VDD
Y2
DATA
Y1
Y0
Data Sheet
40 PIN PLASTIC DIP
Figure 2 - Pin Connections
Change Summary
Changes from the August 2005 issue to the September 2011 issue.
Page
1
Item
Ordering Information
Removed leaded packages as per PCN notice.
Pin Description
Pin #
PDIP
PLCC
Name
1
Y3
Description
1
2
3
4,5
6,7
8-13
14
15
16
17
2
3
4,5
6-8
9-14
15-17
18
-
19
Y3 Analog (Input/Output):
this is connected to the Y3 column of the switch
array.
AY2
Y2 Address Line (Input).
RESET
Master RESET (Input):
this is used to turn off all switches. Active High.
AX3,AX0
X3 and X0 Address Lines (Inputs).
NC
No Connection.
X6-X11
X6-X11 Analog (Inputs/Outputs):
these are connected to the X6-X11 rows of the
switch array.
NC
No Connection.
Y7
Y7 Analog (Input/Output):
this is connected to the Y7 column of the switch
array.
NC
No Connection.
Y6
Y6 Analog (Input/Output):
this is connected to the Y6 column of the switch
array.
2
Zarlink Semiconductor Inc.
Y7
Y6
STROBE
Y5
VSS
Y4
AX1
AX2
AY0
AY1
NC
44 PIN PLCC
Y3
AY2
RESET
AX3
AX0
NC
NC
X6
X7
X8
X9
X10
X11
NC
Y7
NC
Y6
STROBE
Y5
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
Y2
DATA
Y1
NC
Y0
NC
X0
X1
X2
X3
X4
X5
NC
NC
AY1
AY0
AX2
AX1
Y4
NC
NC
X6
XY
X8
X9
X10
X11
NC
NC
NC
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
NC
AX0
NC
NC
X0
X1
X2
X3
X4
X5
NC
NC
NC
Change
MT093
Pin Description
Pin #
PDIP
PLCC
Data Sheet
Name
20
Description
18
19
20
21
22, 23
24, 25
26, 27
28 - 33
34
35
36
37
38
39
40
21
22
23
24,25
26,27
28-31
32-37
38,39
40
-
41
42
43
44
STROBE
STROBE (Input):
enables function selected by address and data. Address must
be stable before STROBE goes high and DATA must be stable on the falling edge
of the STROBE. Active High.
Y5
Y5 Analog (Input/Output):
this is connected to the Y5 column of the switch
array.
Ground Reference.
V
SS
Y4
Y4 Analog (Input/Output):
this is connected to the Y4 column of the switch
array.
AX1,AX2
X1 and X2 Address Lines (Inputs).
AY0,AY1
Y0 and Y1 Address Lines (Inputs).
NC
No Connection.
X5-X0
X5-X0 Analog (Inputs/Outputs):
these are connected to the X5-X0 rows of the
switch array.
NC
No Connection.
Y0
Y0 Analog (Input/Output):
this is connected to the Y0 column of the switch array.
NC
No Connection.
Y1
Y1 Analog (Input/Output):
this is connected to the Y1 column of the switch array.
DATA
DATA (Input):
a logic high input will turn on the selected switch and a logic low will
turn off the selected switch. Active High.
Y2
Y2 Analog (Input/Output):
this is connected to the Y2 column of the switch array.
V
DD
Positive Power Supply.
Functional Description
The MT093 is an analog switch matrix with an array size of 8 x 12. The switch array is arranged such that there are
8 columns by 12 rows. The columns are referred to as the Y input/output lines and the rows are the X input/output
lines. The crosspoint analog switch array will interconnect any X line with any Y line when turned on and provide a
high degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in which the bits
are selected by the address input lines (AY0-AY2, AX0-AX3). Data is presented to the memory on the DATA input
line. Data is asynchronously written into memory whenever the STROBE input is high and is latched on the falling
edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on and a logical
“0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are
altered when data is written into memory. The remaining switches retain their previous states. Any combination of X
and Y lines can be interconnected by establishing appropriate patterns in the control memory. A logical “1” on the
RESET input line will asynchronously return all memory locations to logical “0” turning off all crosspoint switches.
Address Decode
The seven address lines along with the STROBE input are logically ANDed to form an enable signal for the
resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a
location, RESET must be low while the address and data lines are set up. Then the STROBE input is set high and
then low causing the data to be latched. The data can be changed while STROBE is high, however, the
corresponding switch will turn on and off in accordance with the data. Data must be stable on the falling edge of
STROBE in order for correct data to be written to the latch.
3
Zarlink Semiconductor Inc.
MT093
Absolute Maximum Ratings*
- Voltages are with respect to V
SS
unless otherwise stated.
Parameter
1
2
3
4
5
6
Supply Voltage
Analog Input Voltage
Digital Input Voltage
Current on any I/O Pin
Storage Temperature
Package Power Dissipation
PLASTIC DIP
Symbol
V
DD
V
SS
V
INA
V
IN
I
T
S
P
D
-65
Min.
-0.3
-0.3
-0.3
V
SS
-0.3
Data Sheet
Max.
16.0
V
DD
+0.3
V
DD
+0.3
V
DD
+0.3
15
+150
0.6
Units
V
V
V
V
mA
C
W
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions
- Voltages are with respect to V
SS
unless otherwise stated.
Characteristics
1
2
3
4
Operating Temperature
Supply Voltage
Analog Input Voltage
Digital Input Voltage
Sym.
T
O
V
DD
V
INA
V
IN
Min.
0
4.5
V
SS
V
SS
Typ.
25
Max.
70
14.5
3.5
V
DD
Units
C
V
V
V
Test Conditions
DC Electrical Characteristics
†
-
Voltages are with respect to V
SS
=0V, V
DD
=14V unless otherwise stated.
Characteristics
1
Quiescent Supply Current
Sym.
I
DDQ
Min.
Typ.
‡
1
7
2
3
4
5
Off-state Leakage Current
Input Logic “0” level
Input Logic “1” level
Input Leakage (digital pins)
I
OFF
V
IL
V
IH
I
LEAK
2.4
10
Max.
100
15
1
0.8
Units
A
mA
A
V
V
A
All digital inputs at V
IN
= V
SS
or V
DD
Test Conditions
All digital inputs at V
IN
=V
SS
or
V
DD
All digital inputs at V
IN
=2.4V
IV
Xi
- V
Yj
I = V
DD
- V
SS
† DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25
C and are for design aid only; not guaranteed and not subject to production testing.
4
Zarlink Semiconductor Inc.
MT093
DC Electrical Characteristics- Switch Resistance
- V
IDC
/V
ODC
is the external DC offset applied at the analog
I/O pins.
Data Sheet
Characteristics
Sym.
25C
60C
70C
Units
Test Conditions
Typ. Max. Typ. Max. Typ. Max.
1 On-state
V
DD
=14V
Resistance
R
ON
45
65
75
V
SS
=0V,
IV
Xi
-V
Yj
I = 0.25V
V
IDC
=6.75V
V
ODC
=6.5V
V
DD
=14V, V
SS
=0,
V
IDC
=6.75V
V
ODC
=6.5V
IV
Xi
-V
Yj
I = 0.25V
2 Difference in on-state
resistance between two
switches
R
ON
5
10
10
10
AC Electrical Characteristics
†
- Crosspoint Performance
-V
DC
is the external DC offset applied at the analog
I/O pins. Voltages are with respect to V
DD
=7V, V
DC
=0V, V
SS
=-7V, unless otherwise stated.
Characteristics
1
2
3
Switch I/O Capacitance
Feedthrough Capacitance
Frequency Response
Channel “ON”
20LOG(V
OUT
/V
Xi
)=-3dB
Total Harmonic Distortion
Feedthrough
Channel “OFF”
Feed.=20LOG (V
OUT
/V
Xi
)
Crosstalk between any two
channels for switches Xi-Yi and
Xj-Yj.
Xtalk=20LOG (V
Yj
/V
Xi
).
Sym.
C
S
C
F
F
3dB
Min.
Typ.
‡
20
0.2
45
Max.
Units
pF
pF
MHz
Test Conditions
f=1 MHz
f=1 MHz
Switch is “ON”; V
INA
= 2Vpp
sinewave; R
L
= 1k
Switch is “ON”; V
INA
= 2Vpp
sinewave f= 1kHz; R
L
=1k
All Switches “OFF”; V
INA
=
2Vpp sinewave f= 1kHz;
R
L
= 1k.
V
INA
=2Vpp sinewave
f= 10MHz; R
L
= 75.
V
INA
=2Vpp sinewave
f= 10kHz; R
L
= 600.
V
INA
=2Vpp sinewave
f= 10kHz; R
L
= 1k.
V
INA
=2Vpp sinewave
f= 1kHz; R
L
= 10k.
R
L
=1k; C
L
=50pF
4
5
THD
FDT
0.05
-95
%
dB
6
X
talk
-45
-90
-85
-80
dB
dB
dB
dB
50
ns
7
Propagation delay through
switch
t
PS
† Timing is over recommended temperature range.
‡ Typical figures are at 25
C and are for design aid only; not guaranteed and not subject to production testing.
Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5 dB better.
5
Zarlink Semiconductor Inc.
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