MT9040
T1/E1 Synchronizer
Data Sheet
Features
•
•
•
•
Supports AT&T TR62411 and Bellcore GR-1244-
CORE and Stratum 4 timing for DS1 interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and
TBR 13 timing for E1 interfaces
Selectable 19.44 MHz, 1.544MHz, 2.048MHz or
8kHz input reference signals
Provides C1.5, C2, C4, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
Provides 5 different styles of 8 KHz framing
pulses
Attenuates wander from 1.9Hz
Fast lock mode
JTAG Boundary Scan
The MT9040 generates ST-BUS clock and framing
signals that are phase locked to either a 19.44 MHz,
2.048MHz, 1.544MHz, or 8kHz input reference.
The MT9040 is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE, Stratum 4; and ETSI ETS
300 011. It will meet the jitter/wander tolerance, jitter
transfer, intrinsic jitter, frequency accuracy and capture
range for these specifications.
Ordering Information
MT9040AN 48 pin SSOP
-40°C to +85°C
November 2003
Description
The MT9040 T1/E1 System Synchronizer contains a
digital phase-locked loop (DPLL), which provides timing
and synchronization signals for T1 and E1 primary rate
transmission links.
•
•
•
•
Applications
•
•
Synchronization and timing control for multitrunk
T1 and E1 systems
ST-BUS clock and frame pulse source
OSCi
OSCo
FLOCK
LOCK
VDD
VSS
Master Clock
TCK
TDI
TMS
TRST
TDO
IEEE
1149.1a
DPLL
Output
Interface
Circuit
Input
Impairment
Monitor
REF
C19o
C1.5o
C2o
C4o
C6o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
Control State Machine
Feedback
Frequency
Select
MUX
MS
RST
IM
FS1
FS2
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
MT9040
Data Sheet
V
SS
RST
IC
IC
IC
REF
Vdd
OSCo
OSCi
Vss
F16o
F0o
RSP
TSP
F8o
C1.5o
Vdd
LOCK
C2o
C4o
C19o
FLOCK
Vss
IC
1
48
2
47
3
46
45
4
5
44
6
43
42
7
8
41
40
9
10
MT9040AN
39
38
11
12
37
36
13
14
35
34
15
16
33
32
17
31
18
30
19
29
20
21
28
22
27
23
26
24
25
TMS
TCK
TRST
TDI
TDO
IC
IC
FS1
FS2
IC
IC
IC
MS
Vdd
IC
IC
NC
Vss
IC
IM
Vdd
C6o
C16o
C8o
Figure 2 - Pin Connections
Pin Description
Pin #
1,10,
23,31
2
Name
V
SS
RST
Description
Ground.
0 Volts. (Vss pads).
Reset (Input).
A logic low at this input resets the MT9040. To ensure proper operation, the
device must be reset after reference signal frequency changes and power-up. The RST pin
should be held low for a minimum of 300ns. While the RST pin is low, all frame pulses except
RST and TSP and all clock outputs except C6o, C16o and C19o are at logic high. The RST,
TSP, C6o and C16o are at logic low during reset. The C19o is free-running during reset.
Following a reset, the input reference source and output clocks and frame pulses are phase
aligned as shown in Figure 9.
Internal Connection.
Leave open circuit.
Reference (Input).
This is the input reference source (falling edge) used for synchronization.
One of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be used.
Positive Supply Voltage.
+3.3V
DC
nominal.
Oscillator Master Clock (CMOS Output).
For crystal operation, a 20MHz crystal is
connected from this pin to OSCi, see Figure 6. Not suitable for driving other devices. For clock
oscillator operation, this pin is left unconnected, see Figure 5.
Oscillator Master Clock (CMOS Input).
For crystal operation, a 20MHz crystal is connected
from this pin to OSCo, see Figure 6. For clock oscillator operation, this pin is connected to a
clock source, see Figure 5.
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output).
This is an 8kHz 61ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 8.192 Mb/s. See Figure 11.
3,4,5,
38,43
6
7,17
28,35
8
IC
REF
V
DD
OSCo
9
OSCi
11
F16o
2
Zarlink Semiconductor Inc.
MT9040
Pin Description (continued)
Pin #
12
Name
F0o
Description
Data Sheet
Frame Pulse ST-BUS 2.048Mb/s (CMOS Output).
This is an 8kHz 244ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 2.048Mb/s and 4.096Mb/s. See Figure 11.
Receive Sync Pulse (CMOS Output).
This is an 8kHz 488ns active high framing pulse, which
marks the beginning of an ST-BUS frame. This is typically used for connection to the Siemens
MUNICH-32 device. See Figure 12.
Transmit Sync Pulse (CMOS Output).
This is an 8kHz 488ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 12.
Frame Pulse (CMOS Output).
This is an 8kHz 122ns active high framing pulse, which marks
the beginning of a frame. See Figure 11.
Clock 1.544MHz (CMOS Output).
This output is used in T1 applications.
Lock Indicator (CMOS Output).
This output goes high when the PLL is frequency locked to
the input reference.
Clock 2.048MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048Mb/s.
Clock 4.096MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048Mb/s
and 4.096Mb/s.
Clock 19.44MHz (CMOS Output).
This output is used in OC3/STS3 applications.
13
RSP
14
TSP
15
16
18
19
20
21
22
24
25
26
27
29
30
32
33,34,
42
36
37, 39
40
F8o
C1.5o
LOCK
C2o
C4o
C19o
FLOCK
Fast Lock Mode (Input).
Set high to allow the PLL to quickly lock to the input reference (less
than 500 ms locking time).
IC
C8o
C16o
C6o
IM
IC
NC
IC
MS
IC
FS2
Internal Connection.
Tie low for normal operation.
Clock 8.192MHz (CMOS Output).
This output is used for ST-BUS operation at 8.192Mb/s.
Clock 16.384MHz (CMOS Output).
This output is used for ST-BUS operation with a
16.384MHz clock.
Clock 6.312 Mhz (CMOS Output).
This output is used for DS2 applications.
Impairment Monitor (CMOS Output).
A logic high on this pin indicates that the Input
Impairment Monitor has automatically put the device into Freerun Mode.
Internal Connection.
Tie high for normal operation.
No Connection.
Leave open circuit.
Internal Connection.
Tie low for normal operation.
Mode/Control Select (Input).
This input determines the state (Normal or Freerun) of
operation. The logic level at this input is gated in by the rising edge of F8o. See Table 2.
Internal Connection.
Tie low for normal operation.
Frequency Select 2 (Input).
This input, in conjunction with FS1, selects which of four possible
frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the REF input. See
Table 1.
Frequency Select 1 (Input).
See pin description for FS2.
Test Serial Data Out (CMOS Output).
JTAG serial data is output on this pin on the falling
edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.
41
44
FS1
TDO
3
Zarlink Semiconductor Inc.
MT9040
Pin Description (continued)
Pin #
45
46
47
48
Name
TDI
TRST
TCK
TMS
Description
Data Sheet
Test Serial Data In (Input).
JTAG serial test instructions and data are shifted in on this pin.
This pin is internally pulled up to V
DD
.
Test Reset (Input).
Asynchronously initializes the JTAG TAP controller by putting it in the
Test-Logic-Reset state. If not used, this pin should be held low.
Test Clock (Input).
Provides the clock to the JTAG test logic.
Test Mode Select (Input).
JTAG signal that controls the state transitions of the TAP controller.
Functional Description
The MT9040 is a T1/E1 Trunk Synchronizer, providing timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block diagram which
is described in the following sections.
Frequency Select MUX Circuit
The MT9040 operates on the falling edge of the reference. It operates with one of four possible input reference
frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). The frequency select inputs (FS1 and FS2) determine
which of the four frequencies may be used at the reference input. A reset (RST) must be performed after every
frequency select input change. See Table 1.
FS2
0
0
1
1
FS1
0
1
0
1
Input Frequency
19.44MHz
8kHz
1.544MHz
2.048MHz
Table 1 - Input Frequency Selection
Digital Phase Lock Loop (DPLL)
As shown in Figure 3, the DPLL of the MT9040 consists of a Phase Detector, Loop Filter, Digitally Controlled
Oscillator and a Control Circuit.
Phase Detector
- the Phase Detector compares the reference signal with the feedback signal from the Frequency
Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This error
signal is passed to the Loop Filter. The Frequency Select MUX allows the proper feedback signal to be externally
selected (e.g., 8kHz, 1.544MHz, 2.048MHz or 19.44MHz).
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Zarlink Semiconductor Inc.
MT9040
Data Sheet
Reference
Phase
Detector
Loop Filter
Digitally
Controlled
Oscillator
DPLL Reference
to
Output Interface Circuit
Feedback Signal
from
Frequency Select MUX
State Select
from
Input Impairment Monitor
Control
Circuit
State Select
from
State Machine
Figure 3 - DPLL Block Diagram
Loop Filter
- the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four
reference frequency selections (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). This filter ensures that the network
jitter transfer requirements are met.
Control Circuit
- the Control Circuit uses status and control information from the State Machine and the Input
Impairment Circuit to set the mode of the DPLL. The two possible modes are Normal and Freerun.
Digitally Controlled Oscillator (DCO)
- the DCO receives the filtered signal from the Loop Filter, and based on its
value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on
the state of the MT9040.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the input reference
sinal.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source.
Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical to
the line frequency), and the input phase offset is small, then the lock signal will be set high. For specific Lock
Indicator design recommendations, see the Applications - Lock Indicator section.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure
4. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1 Divider Circuit,
and a DS2 Divider Circuit to generate the required output signals.
Four tapped delay lines are used to generate 16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz signals.
The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and five frame pulse outputs. The
C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.
These outputs have a nominal 50% duty cycle.
The T1 Divider Circuit uses the 12.384MHz signal to generate the C1.5o clock by dividing the internal C12 clock
by eight. This output has a nominal 50% duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal
50% duty cycle.
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