MT9043
T1/E1 System Synchronizer
Preliminary Information
Features
•
Supports AT&T TR62411 and Bellcore GR-
1244-CORE, Stratum 4 Enhanced and Stratum
4 timing for DS1 interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12
and TBR 13 timing for E1 interfaces
Selectable 19.44 MHz, 1.544MHz, 2.048MHz or
8kHz input reference signals
Provides C1.5, C2, C4, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
Provides 5 different styles of 8 KHz framing
pulses
Attenuates wander from 1.9Hz
Fast lock mode
Provides Time Interval Error (TIE) correction
Accepts reference inputs from two independent
sources
JTAG Boundary Scan
DS5343
ISSUE 1
February 2000
Ordering Information
MT9043AN
48 Pin SSOP
-40 to +85
°C
•
•
•
Description
The MT9043 T1/E1 System Synchronizer contains a
digital phase-locked loop (DPLL), which provides
timing and synchronization signals for multitrunk T1
and E1 primary rate transmission links.
The MT9043 generates ST-BUS clock and framing
signals that are phase locked to either a 19.44 MHz,
2.048MHz, 1.544MHz, or 8kHz input reference.
The MT9043 is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE, Stratum 4 Enhanced, and
Stratum 4; and ETSI ETS 300 011. It will meet the
jitter/wander tolerance, jitter transfer, intrinsic jitter,
frequency accuracy, capture range, phase change
slope,
and
MTIE
requirements
for
these
specifications.
•
•
•
•
•
•
Applications
•
•
Synchronization and timing control for
multitrunk T1,E1 and STS-3/OC3 systems
ST-BUS clock and frame pulse sources
OSCi
OSCo
TCLR
LOCK
VDD
VSS
Master Clock
TCK
TDI
TMS
TRST
TDO
PRI
SEC
IEEE
1149.1a
TIE
Corrector
Circuit
Virtual
Reference
DPLL
Output
Interface
Circuit
Reference
Select
MUX
Selected
Reference
TIE
Corrector
Enable
State
Select
Input
Impairment
Monitor
Reference
Select
RSEL
Control State Machine
State
Select
C19o
C1.5o
C2o
C4o
C6o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
Feedback
Frequency
Select
MUX
MS
RST
IM
FLOCK
FS1
FS2
Figure 1 - Functional Block Diagram
1
MT9043
Preliminary Information
V
SS
RST
TCLR
IC
SEC
PRI
Vdd
OSCo
OSCi
Vss
F16o
F0o
RSP
TSP
F8o
C1.5o
Vdd
LOCK
C2o
C4o
C19o
FLOCK
Vss
IC
1
48
2
47
3
46
45
4
5
44
6
43
42
7
8
41
40
9
10
MT9043AN
39
38
11
12
37
36
13
14
35
34
15
16
33
17
32
31
18
30
19
29
20
21
28
22
27
26
23
24
25
TMS
TCK
TRST
TDI
TDO
IC
IC
FS1
FS2
IC
RSEL
MS
IC
Vdd
IC
IC
NC
Vss
IC
IM
Vdd
C6o
C16o
C8o
Figure 2 - Pin Connections
Pin Description
Pin #
1,10,
23,31
2
Name
V
SS
RST
Ground.
0 Volts. (Vss pads).
Reset (Input).
A logic low at this input resets the MT9043. To ensure proper operation, the
device must be reset after changes to the method of control, reference signal frequency
changes and power-up. The RST pin should be held low for a minimum of 300ns. While the
RST pin is low, all frame and clock outputs are at logic high. Following a reset, the input
reference source and output clocks and frame pulses are phase aligned as shown in Figure
11.
TIE Circuit Reset (Input).
A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a realignment of input phase with output phase as shown in
Figure 11. The TCLR pin should be held low for a minimum of 300ns. This pin is internally
pulled down to VSS.
Internal Connection.
Leave open circuit.
Secondary Reference (Input).
This is one of two (PRI & SEC) input reference sources
(falling edge) used for synchronization. One of four possible frequencies (8kHz, 1.544MHz,
2.048MHz or 19.44MHz) may be used. The selection of the input reference is based upon
the MS, and RSEL, control inputs.This pin is internally pulled up to V
DD
.
Primary Reference (Input).
See pin description for SEC. This pin is internally pulled up to
V
DD
.
Positive Supply Voltage.
+3.3V
DC
nominal.
Oscillator Master Clock (CMOS Output).
For crystal operation, a 20MHz crystal is
connected from this pin to OSCi, see Figure 8. For clock oscillator operation, this pin is left
unconnected, see Figure 7.
Oscillator Master Clock (CMOS Input).
For crystal operation, a 20MHz crystal is
connected from this pin to OSCo, see Figure 8. For clock oscillator operation, this pin is
connected to a clock source, see Figure 7.
Description
3
TCLR
4
5
IC
SEC
6
7,17
28,35
8
PRI
V
DD
OSCo
9
OSCi
2
Preliminary Information
Pin Description
Pin #
11
Name
F16o
Description
MT9043
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output).
This is an 8kHz 61ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 8.192 Mb/s. See Figure 12.
Frame Pulse ST-BUS 2.048Mb/s (CMOS Output).
This is an 8kHz 244ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 2.048Mb/s and 4.096Mb/s. See Figure 12.
Receive Sync Pulse (CMOS Output).
This is an 8kHz 488ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 13.
Transmit Sync Pulse (CMOS Output).
This is an 8kHz 488ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 13.
Frame Pulse (CMOS Output).
This is an 8kHz 122ns active high framing pulse, which
marks the beginning of a frame. See Figure 12.
Clock 1.544MHz (CMOS Output).
This output is used in T1 applications.
Lock Indicator (CMOS Output).
This output goes high when the PLL is frequency locked
to the input reference.
Clock 2.048MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048Mb/s.
Clock 4.096MHz (CMOS Output).
This output is used for ST-BUS operation at 2.048Mb/s
and 4.096Mb/s.
Clock 19.44MHz (CMOS Output).
This output is used in OC3/STS3 applications.
Fast Lock Mode (Input).
Set high to allow the PLL to quickly lock to the input reference
(less than 500 ms locking time).
Internal Connection.
Leave Open Circuit.
Clock 8.192MHz (CMOS Output).
This output is used for ST-BUS operation at 8.192Mb/s.
Clock 16.384MHz (CMOS Output).
This output is used for ST-BUS operation with a
16.384MHz clock.
Clock 6.312 Mhz (CMOS Output).
This output is used for DS2 applications.
Impairment Monitor (CMOS Output).
A logic high on this pin indicates that the Input
Impairment Monitor has automatically put the device into Freerun Mode.
Internal Connection.
Tie high for normal operation.
No Connection.
Leave open circuit.
Internal Connection.
Tie low for normal operation.
Internal Connection.
Tie low for normal operation.
Mode/Control Select (Input).
This input determines the state (Normal or Freerun) of
operation. The logic level at this input is gated in by the rising edge of F8o. See Table 3.
This pin is internally pulled down to VSS.
Reference Source Select (Input).
A logic low selects the PRI (primary) reference source
as the input reference signal and a logic high selects the SEC (secondary) input. The logic
level at this input is gated in by the rising edge of F8o. See Table 2. This pin is internally
pulled down to VSS.
Internal Connection.
Leave Open Circuit.
12
F0o
13
RSP
14
TSP
15
16
18
19
20
21
22
24
25
26
27
29
30
32
33,34
36
37
F8o
C1.5o
LOCK
C2o
C4o
C19o
FLOCK
IC
C8o
C16o
C6o
IM
IC
NC
IC
IC
MS
38
RSEL
39
IC
3
MT9043
Pin Description
Pin #
40
Name
FS2
Description
Preliminary Information
Frequency Select 2 (Input).
This input, in conjunction with FS1, selects which of four
possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI
and SEC inputs. See Table 1.
Frequency Select 1 (Input).
See pin description for FS2.
Internal Connection.
Tie Low for Normal Operation.
Internal Connection.
Leave Open Circuit.
Test Serial Data Out (CMOS Output).
JTAG serial data is output on this pin on the falling
edge of TCK. This pin is held in high impedance state when JTAG scan is not enable.
Test Serial Data In (Input).
JTAG serial test instructions and data are shifted in on this pin.
This pin is internally pulled up to V
DD
.
Test Reset (Input).
Asynchronously initializes the JTAG TAP controller by putting it in the
Test-Logic-Reset state. This pin is internally pulled down to VSS.
Test Clock (Input).
Provides the clock to the JTAG test logic. This pin is internally pulled up
to V
DD
.
Test Mode Select (Input).
JTAG signal that controls the state transitions of the TAP
controller. This pin is internally pulled up to V
DD
.
41
42
43
44
45
46
47
48
FS1
IC
IC
TDO
TDI
TRST
TCK
TMS
4
Preliminary Information
Functional Description
FS2
The MT9043 is a Multitrunk System Synchronizer,
providing timing (clock) and synchronization (frame)
signals to interface circuits for T1 and E1 Primary
Rate Digital Transmission links. Figure 1 is a
functional block diagram which is described in the
following sections.
Reference Select MUX Circuit
0
0
1
1
FS1
0
1
0
MT9043
Input Frequency
19.44MHz
8kHz
1.544MHz
1
2.048MHz
Table 1 - Input Frequency Selection
Time Interval Error (TIE) Corrector Circuit
The MT9043 accepts two simultaneous reference
input signals and operates on their falling edges.
Either the primary reference (PRI) signal or the
secondary reference (SEC) signal can be selected
as input to the TIE Corrector Circuit. The selection is
based on the Control, Mode and Reference
Selection of the device. See Table 1 and Table 4.
Frequency Select MUX Circuit
The MT9043 operates with one of four possible input
reference frequencies (8kHz, 1.544MHz, 2.048MHz
or 19.44MHz). The frequency select inputs (FS1 and
FS2) determine which of the four frequencies may
be used at the reference inputs (PRI and SEC). Both
inputs must have the same frequency applied to
them. A reset (RST) must be performed after every
frequency select input change. See Table 1.
The TIE corrector circuit, when enabled, prevents a
step change in phase on the input reference signals
(PRI or SEC) from causing a step change in phase at
the input of the DPLL block of Figure 1.
During reference input rearrangement, such as
during a switch from the primary reference (PRI) to
the secondary reference (SEC), a step change in
phase on the input signals will occur. A phase step at
the input of the DPLL would lead to unacceptable
phase changes in the output signal.
As shown in Figure 3, the TIE Corrector Circuit
receives one of the two reference (PRI or SEC)
signals, passes the signal through a programmable
delay line, and uses this delayed signal as an
internal virtual reference, which is input to the DPLL.
Therefore, the virtual reference is a delayed version
of the selected reference.
During a switch from one reference to the other, the
State Machine first changes the mode of the device
TCLR
Resets Delay
Control
Circuit
Control Signal
Delay Value
PRI or SEC
from
Reference
Select Mux
Programmable
Delay Circuit
Virtual
Reference
to DPLL
Compare
Circuit
TIE Corrector
Enable
from
State Machine
Feedback
Signal from
Frequency
Select MUX
Figure 3 - TIE Corrector Circuit
5
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