CMOS ST-BUS
TM
Family
MT8986
Multiple Rate Digital Switch
Data Sheet
Features
•
•
•
•
•
•
•
•
•
•
•
256 x 256 or 512 x 256 switching configurations
8-bit or 4-bit channel switching capability
Guarantees frame integrity for wideband
channels
Automatic identification of ST-BUS/GCI interfaces
Accepts serial streams with data rates up to
8.192 Mb/s
Rate conversion from 2.048 Mb/s to 4.096 or
8.192 Mb/s and vice-versa
Programmable frame offset on inputs
Per-channel three-state control
Per-channel message mode
Control interface compatible to Intel/Motorola
CPUs
Low power consumption
November 2005
Ordering Information
MT8986AE
40 Pin PDIP
Tubes
MT8986AP
44 Pin PLCC
Tubes
MT8986AL
44 Pin MQFP
Trays
MT8986APR
44 Pin PLCC
Tape & Reel
MT8986AP1
44 Pin PLCC*
Tubes
MT8986APR1
44 Pin PLCC*
Tape & Reel
MT8986AL1
44 Pin MQFP*
Trays
MT8986AE1
40 Pin PDIP*
Tubes
*Pb Free Matte Tin
-40°C to +85°C
Description
The Multiple Rate Digital Switch (MRDX) is an
upgraded version of Zarlink's MT8980D Digital Switch
(DX). It is pin compatible with the MT8980D and
retains all of its functionality. This device is designed to
provide simultaneous connections (non-blocking) for
up to 256 64 kb/s channels or blocking connections for
up to 512 64 kb/s channels. The serial inputs and
outputs connected to MT8986 may have 32 to 128
64 kb/s channels per frame with data rates ranging
from 2048 up to 8192 kb/s. The MT8986 provides per-
channel selection between variable and constant
throughput delays allowing voice and grouped data
channels to be switched without corrupting the data
sequence integrity.
In addition, the MT8986 can be used for switching of
32 kb/s channels in ADPCM applications. The MT8986
is ideal for medium size mixed voice and data
switching/processing applications.
V
DD
V
SS
ODE
Applications
•
•
•
•
•
•
•
Medium size digital switch matrices
Hyperchannel switching (e.g., ISDN H0)
MVIP
™
interface functions
Serial bus control and monitoring
Centralized voice processing systems
Voice/Data multiplexer
32 kbit/s channel switching
*
*
*
*
*
*
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
Serial
to
Parallel
Converter
Timing
Unit
Multiple Buffer Data
Memory
Output
MUX
Parallel
to
Serial
Converter
Connection
Memory
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8 *
STo9 *
Internal Registers
Microprocessor
Interface
* 44 Pin only
CLK FR AS/ IM
ALE *
DS CS
RD
R/W A0/ DTA AD7/
AD0
WR A7
CSTo
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT8986
AS/ALE
STi2
STi1
STi0
DTA
CSTo
ODE
STo0
STo1
STo2
STi4/STo8
AS/ALE
STi2
STi1
STi0
DTA
CSTo
ODE
STo0
STo1
STo2
STi4/STo8
STo3
STo4
STo5
STo6/A6
STo7/A7
VSS
AD0
AD1
AD2
AD3
AD4
STi3
STi4
STi5
STi6/A6
STi7/A7
VDD
FR
CLK
STi8/A0
STi9/A1
STi10/A2
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
Data Sheet
STi3
STi4
STi5
STi6/A6
STi7/A7
VDD
FR
CLK
STi8/A0
STi9/A1
STi10/A2
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
IM
STi11/A3
STi12/A4
STi3/A5
DS/RD
R/W/WR
CS
AD7
AD6
AD5
STi15/STo9
STo3
STo4
STo5
STo6/A6
STo7/A7
VSS
AD0
AD1
AD2
AD3
AD4
44 PIN PLCC
DTA
STi0
STi1
STi2
STi3
STi4
STi5
STi6/A6
STi7/A7
VDD
FR
CLK
A0
A1
A2
A3
A4
A5
DS/RD
R/W\WR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 PIN DIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CSTo
ODE
STo0
STo1
STo2
STo3
STo4
STo5
STo6/A6
STo7/A7
VSS
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
CS
Figure 2 - Pin Connections
2
Zarlink Semiconductor Inc.
IM
STi11/A3
STi12/A4
STi3/A5
DS/RD
R/W/WR
CS
AD7
AD6
AD5
STi15/STo9
44 PIN QFP
12
13
14
15
16
17
18
19
20
21
22
MT8986
Pin Description
Pin #
40
DIP
44
PLCC
44
QFP
Data Sheet
Name
Description
1
2
40
DTA
Data Acknowledgement
(Open Drain Output). This active low output indicates
that a data bus transfer is complete. A 10 kΩ pull-up resistor is required at this
output.
ST-BUS Inputs 0 to 5
(Inputs). Serial data input streams. These streams may
have data rates of 2.048, 4.096 or 8.192 Mbit/s with 32, 64 or 128 channels,
respectively.
2-7
3-5
7-9
10
41-43
1-3
4
STi0-5
8
STi6/A6
ST-BUS Input 6/Addr.6 input
(Input). The function of this pin is determined by
the switching configuration enabled. If non-multiplexed CPU bus is used along
with a higher input rate of 8.192 or 4.096 Mb/s, this pin provides A6 address
input function. For 2.048 and 4.096 Mb/s (8x4) applications or when multiplexed
CPU bus (44 pin only) is selected, this pin assumes STi6 function. See Control
Register bits description and Tables 1, 2, 6 & 7 for more details.
Note that for applications where both A6 and STi6 inputs are required
simultaneously (e.g., 8 x 4 switching configuration at 4.096 Mb/s or rate
conversion between 2.048 Mb/s to 4.196 or 8.192 Mb/s) the A6 input should be
connected to pin STo6/A6.
STi7/A7
ST-BUS Input 7/Addr.7 input
(Input): The function of this pin is determined by
the switching configuration enabled. If non-multiplexed CPU bus is used along
with a higher input rate of 8.192 Mb/s, this pin provides A7 address input
function.
For 2.048 and 4.096 Mb/s (8x4) applications or when multiplexed CPU bus
(44 pin only) is selected, this pin assumes STi7 function. See Control Register
bits description and Tables 1, 2, 6 & 7 for more details.
Note that for applications where both A7 and STi7 inputs are required
simultaneously (e.g., 2.048 to 8.192 Mb/s rate conversion) the A7 input should
be connected to pin STo7/A7.
V
DD
FR
+5 Volt Power Supply.
Frame Pulse
(Input). This input accepts and automatically identifies frame
synchronization signals formatted according to ST-BUS and GCI interface
specifications.
Clock
(Input). Serial clock for shifting data in/out on the serial streams.
Depending on the serial interface speed selected by IMS (Interface Mode Select)
register, the clock at this pin can be 4.096 or 8.192 MHz.
9
11
5
10
11
12
13
6
7
12
14
8
CLK
13-15 15-17
9-11
A0-2/
Address 0-2 / Input Streams 8-10
(Input). When non-multiplexed CPU bus is
STi8-10
selected, these lines provide the A0-A2 address lines to MT8986 internal
registers. When 16x8 switching configuration is selected (in 44 pin only), then
these pins are ST-BUS serial inputs 8 to 10 receiving data at 2.048 Mb/s.
A3-5/
Address 3-5 / Input Streams 11-13
(Input). When non-multiplexed CPU bus is
STi11-13
selected, these lines provide the A3-A5 address lines to MT8986 internal
registers. When 16x8 switching configuration is selected (in 44 pin only), then
these pins are ST-BUS serial inputs 11 to 13 receiving data at 2.048 Mb/s.
16-18 19-21 13-15
3
Zarlink Semiconductor Inc.
MT8986
Pin Description (continued)
Pin #
40
DIP
44
PLCC
44
QFP
Data Sheet
Name
Description
19
22
16
DS/RD
Data Strobe/Read
(Input). When non-multiplexed CPU bus or Motorola
multiplexed bus (44 pin only) are selected, this input is DS. This active high input
works in conjunction with CS to enable read and write operation.
For Intel/National multiplexed bus (44 pin only), this input is RD. This active low
input configures the data bus lines (AD0-AD7) as outputs.
R/W\WR
Read/Write \ Write
(Input). In case of non-multiplexed and Motorola multiplexed
buses (44 pin only), this input is R/W. This input controls the direction of the data
bus lines (AD0-AD7) during a microprocessor access.
With Intel/National multiplexed timing (44 pin only), this input is WR. This active
low signal configures the data bus lines (AD0-AD7) as inputs.
CS
AD7-
AD0
Chip Select
(Input). Active low input enabling a microprocessor read or write of
the control register or internal memories.
Data Bus
(Bidirectional): These pins provide microprocessor access to the
internal control registers, connection memories high and low and data memories.
In multiplexed bus mode (44 pin) these pins also provide the input address to the
internal Address Latch circuit.
Ground.
20
23
17
21
24
18
22-29 25-27 19-21
29-33 23-27
30
31
34
35
28
29
V
SS
STo7/A7
ST-BUS Output 7/Address 7 input
(Three-state output/input). The function of
this pin is determined by the switching configuration enabled. If non-multiplexed
CPU bus is used along with data rates employing 8.192 Mb/s rates, this pin
provides A7 address input function. For 2.048 Mb/s applications or when
multiplexed CPU bus (44 pin only) is selected, this pin assumes STo7 function.
See Tables 1, 2, 6 & 7 for more details.
Note that for applications where A7 input and STo7 output are required
simultaneously (e.g., 8.192 to 2.048 Mb/s rate conversion), the A7 input should
be connected to pin STi7/A7.
32
36
30
STo6/A6
ST-BUS Output 6/Address 6 input
(Three-state output/input). The function of
this pin is determined by the switching configuration enabled. If non-multiplexed
CPU bus is used along with a higher data rate employing 8.192 or 4.096 Mb/s,
this pin provides the A6 address input function. For 2.048 Mb/s applications or
when multiplexed CPU bus (44 pin only) is selected, this pin assumes STo6
function. See Tables 1, 2, 6 & 7 for more details.
Note that for applications where both A6 input and STo6 output are required
simultaneously (e.g., 4.096 to 2.048 Mb/s or 8.192 to 2.048 Mb/s rate conversion
applications), the A6 input should be connected to pin STi6/A6.
STo5-0
ST-BUS Outputs 5 to 0
(Three-state Outputs). Serial data output streams.
These serial streams may be composed of 32, 64 and 128 channels at data rates
of 2.048, 4.096 or 8.192 Mbit/s, respectively.
ODE
Output Drive Enable
(Input). This is the output enable input for the STo0 to
STo9 serial outputs. If this input is low STo0-9 are high impedance. If this input
is high each channel may still be put into high impedance by using per-channel
control bits in Connect Memory High.
33-38 37-39 31-33
41-43 35-37
39
44
38
4
Zarlink Semiconductor Inc.
MT8986
Pin Description (continued)
Pin #
40
DIP
44
PLCC
44
QFP
Data Sheet
Name
Description
40
1
39
CSTo
Control ST-BUS Output
(Output). This is a 2.048 Mb/s output containing 256
bits per frame. The level of each bit is determined by the CSTo bit in the Connect
Memory high locations.
-
6
44
AS/ALE
Address Strobe or Latch Enable
(Input). This input is only used if multiplexed
bus is selected via the IM input pin (44 pin only).
The falling edge of this signal is used to sample the address into the address
latch circuit. In case of non-multiplexed bus, this input is not required and should
be left open.
IM
CPU Interface Mode
(Input). If HIGH, this input configures MT8986 in
multiplexed microprocessor bus mode. If this input pin is not connected or
grounded, the MT8986 assumes non-multiplexed CPU interface.
ST-BUS Input 15 / ST-BUS Output 9
(Input/three-state output). This pin is only
used if multiplexed CPU bus is selected. If 16-input x 8-output switching
configuration is enabled in the SCB bits (IMS register), this pin is an input
receiving serial ST-BUS stream 15 at a data rate of 2.048 Mbit/s.
If Stream Pair Selection capability is enabled (see switching configuration
section), this pin is the ST-BUS stream 9 output.
When non-multiplexed bus structure is used, this pin should be left open.
ST-BUS Input 14 / ST-BUS Output 8
(Input/three-state output). This pin is only
used if multiplexed CPU bus is selected. If 16-input x 8-output switching
configuration is enabled in the SCB bits (IMS register), this pin is an input that
receives serial ST-BUS stream 14 at a data rate of 2.048 Mbit/s.
If Stream Pair Selection capability is enabled (see switching configuration
section), this pin is the ST-BUS stream 8 output.
When non-multiplexed bus structure is used, this pin should be left open.
-
18
12
-
28
22
STi15/
STo9
-
40
34
STi14/
STo8
Device Overview
With the integration of voice, video and data services in the same network, there has been an increasing demand
for systems which ensure that data at N x 64 kbit/s rates maintain sequence integrity while being transported
through time-slot interchange circuits. This requirement demands time-slot interchange devices which perform
switching with constant throughput delay for wideband data applications while guaranteeing minimum delay for
voice channels.
The MT8986 device meets the above requirement and allows existing systems based on the MT8980D to be easily
upgraded to maintain the data integrity when wideband data is transported. The device is designed to switch 32, 64
or N x 64 kbit/s data. The MT8986 can provide frame integrity for data applications and minimum throughput
switching delay for voice applications on a per channel basis.
The serial streams of the MT8986 device can operate at 2.048, 4.096 or 8.192 Mbit/s and are arranged in 125
µs
wide frames which contain 32, 64 and 128 channels, respectively. In addition, a built-in rate conversion circuit
allows the user to interconnect various backplane speeds like 2.048 or 4.096 or 8.192 Mb/s while maintaining the
control of throughput delay function on a per-channel basis.
By using Zarlink Message mode capability, the microprocessor can access input and output time-slots on a per
channel basis to control external circuits or other ST-BUS devices. The MT8986 automatically identifies the polarity
5
Zarlink Semiconductor Inc.
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