CB664
I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM
Approved Product
Product Features
•
•
•
•
•
•
7 output buffer for high clock fanout applications.
2
Output may be individually disabled with I C
VDD = 3.3 volts
Output frequency range 10 MHz to 100 MHz
<250ps skew between output clocks.
16-pin SSOP and TSSOP package.
Product Description
The device is a high fanout system clock buffer. Its
primary application is to distribute clocks needed to
support a wide range of applications such as SDRAM
clocks. This device provides low skew distribution
clock heavily loaded. One important application of
this component is where long traces are used to
transport clocks from their generating devices to their
loads. The creation of EMI and the degradation of
waveform rise and fall times is greatly reduces by
running a single reference clock trace to this device
and then using it to these devices EMI is therefore
minimized and board real estate is saved.
Block Diagram
Pin Configuration
VDD
I
2
C Control
2
SDATA
SCLK
SDR(0:1)
VDD
SDR0
SDR1
VSS
CLKIN
SDR2
VDD
SDATA
1
SDR2
SDR(3:4)
SDR(5:6)
REFIN
2
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SDR6
SDR5
VSS
VDD
SDR4
SDR3
VSS
SCLK
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07024 Rev. **
5/6/99
Page 1 of 8
CB664
I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM
Approved Product
Pin Description
Pin No.
5
2,3,6,11,12,15,16
8
9
4,10,14
1,7,13
Pin Name
CLKIN
SDR(0:6)
SDATA
SCLK
VSS
VDD
PWR
VDD
VDD
-
-
-
-
I/O
I
O
I/O
I
-
-
Type
PAD
BUF1
PAD
PAD
-
-
Description
This pin is connected to the input reference clock.
This clock be in the range of 10.0 to 100.0 MHz
Low Skew output clock.
2
Serial data of I C-wire control interface. Has internal
pull-up resistor.
2
Serial data of I C-wire control interface. Has internal
pull-up resistor
COMMON Ground
Power for output clock buffers and core logic
Maximum Ratings
Maximum Input Voltage Relative to VSS: VSS – 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
0 to +125 C
0 to +70 C
7V
o
o
o
o
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07024 Rev. **
5/6/99
Page 2 of 8
CB664
I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM
Approved Product
2-Wire I
2
C Control Interface
The 2-wire control interface implements a write only slave interface. The device control be read back. Sub-
addressing is not supported, thus, all preceding bytes must be sent in order to change one of the control bytes.
The 2-wire control interface allows each clock output to be individually enabled or disabled.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when
SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used
to indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the
end of data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated.
The first byte of a transfer cycle is a 7-bit address with a read /write bit as the LSB. Data is being transferred MSB
first.
The device respond to writes to 10 bytes (max) of data to address
D2
by generating the acknowledge (low) signal
on the SDATA wire following reception of each byte. The device will not respond to any other control interface
conditions.
Control Signal Registers
Note:
The pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is
activated.
Following the acknowledge of the Address Byte (D2) two additional bytes must be sent:
1.
“Command
Code”
byte and
2.
“Byte Count”
byte
Although the data (bits) in these two bytes are considered “ don’t care”, they must be sent and will be
acknowledge.
After the Command Code and the Count bytes have been acknowledge, the below described sequence (Byte0,
Byte1, Byte2…) will be valid and acknowledged.
Byte 0:
(1= Enable, 0= stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin #
6
-
-
-
3
2
-
-
Description
SDR2(Enable =1,stopped=0)
Reserved
Reserved
Reserved
SDR1(Enable =1,stopped=0)
SDR0(Enable =1,stopped=0)
Reserved
Reserved
Byte 1:
(1= Enable, 0= stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin #
16
15
-
-
12
11
-
-
Description
SDR6 (enable=1,s topped=0)
SDR5 (enable=1, stopped=0 )
Reserved
Reserved
SDR4 (enable=1, stopped=0)
SDR3 (enable=1, stopped=0)
Reserved
Reserved
See application note AN664-01 for further reducing power
consumption with I
2
C
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07024 Rev. **
5/6/99
Page 3 of 8
CB664
I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM
Approved Product
Electrical Characteristics
Characteristics
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Tri-State leakage current
Dynamic Supply Current (all
outputs loaded with 30 pF)
Static Supply Current
Short Circuit Current
Input Rise Time
Symbol
VIL
VIH
IIL
IIH
Ioz
Idd
66
Idd
100
Isdd
Min
-
2.0
-66
-
9
12
-
Typ
-
-
Max
0.8
-
66
10
100
140
1
Units
Vdc
Vdc
µA
µA
µA
mA
mA
mA
Conditions
-
-
-
Input Frequency = 66 Mhz
-
Input Frequency =100 Mhz
-
All outputs disabled no input
clock
ISC
25
-
-
mA
1 input at a time – 30 seconds
VIR
2.4
-
-
nS
0.8 to 2.4 Volts
VDD =VDD1 thru VDD6 = 3.3V±5%, TA = 0°C to 70°C
±
°
°
Switching Characteristics
Characteristics
Output Duty Cycle
Buffer Out/Out Skew all Buffer
Outputs
Buffer Input to Output Skew
Jitter Cycle to Cycle*
Jitter Absolute (Peak to Peak)*
Symbol
-
TSKEW
Min
45
-
Typ
50
-
Max
55
250
Units
%
pS
Conditions
Measured at 1.5V (50/50 in)
35 pF Load Measured at 1.5V
TSKEW
2.0
0
5.0
nS
TJCC
50
pS
@35 pF loading
TJabs
150
pS
@35 pF loading
VDD =VDD1 thru VDD6 = 3.3V±5%, TA = 0°C to 70°C
±
°
°
*
this jitter is additive to the input clock’s jitter
Buffer Characteristics ( All Clock Outputs)
Characteristics
Pull-Up Current Min
ull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
Rise/Fall Time Min
Between 0.4V and 2.4V
Rise/Fall Time Max
between 0.4V and 2.4V
Symbol
IOH
min
IOH
max
IOL
min
IOL
max
TRF
min
TRF
max
Min
-
-
-
-
-
-
Typ
-
-
-
-
-
-
Max
-54
30
54
23
1.33
1.33
Units
mA
mA
mA
mA
nS
nS
Conditions
Vout = 1.0 V
Vout = 2.6 V
Vout = 1.2 V
Vout = 0.4 V
30 pF Load
30 pF Load
VDD = VDDI thru VDD6 = 3.3V±5%, TA = 0°c TO +70°C
±
°
°
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07024 Rev. **
5/6/99
Page 4 of 8
CB664
I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM
Approved Product
PCB Layout Suggestion
Via to VDD Plane
Via to GND Plane
C1
1
2
3
4
5
6
16
15
14
13
12
11
10
9
Void (Cut) in power plane
FBI or R1
C3
VCC
C2
7
8
C7
6.8 to 22µF
This is only a layout recommendation for best performance and lower EMI. The designer may choose a different
approach but C1, C2, C3 (all are o.1µF) should always be used and placed as close to their VDD pins as is
physically possible. FB1 or R1 is a ferrite Bead or resistor as needed to reduce conducted EMI from the device
into the systems power circuitry.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07024 Rev. **
5/6/99
Page 5 of 8
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