NDD04N50Z
N-Channel Power MOSFET
500 V, 2.7
W
Features
•
•
•
•
•
Low ON Resistance
Low Gate Charge
ESD Diode−Protected Gate
100% Avalanche Tested
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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V
DSS
500 V
R
DS(on)
(MAX) @ 1.5 A
2.7
W
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Continuous Drain Current R
qJC
Continuous Drain Current
R
qJC
, T
A
= 100°C
Pulsed Drain Current, V
GS
@ 10 V
Power Dissipation R
qJC
Gate−to−Source Voltage
Single Pulse Avalanche Energy,
I
D
= 3.4 A
ESD (HBM) (JESD22−A114)
Peak Diode Recovery
Continuous Source Current
(Body Diode)
Maximum Temperature for Soldering
Leads
Operating Junction and
Storage Temperature Range
Symbol
V
DSS
I
D
I
D
I
DM
P
D
V
GS
E
AS
V
esd
dv/dt
I
S
T
L
T
J
, T
stg
Value
500
3.0
1.9
12
61
±30
120
2800
4.5 (Note 1)
3.4
260
−55
to 150
Unit
V
A
A
A
W
V
mJ
V
V/ns
A
°C
°C
1
2
1 2
3
3
4
4
S (3)
G (1)
N−Channel
D (2)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. I
D
v
3.4 A, di/dt
≤
200 A/ms, V
DD
≤
BV
DSS
, T
J
≤
150°C.
IPAK
CASE 369D
STYLE 2
DPAK
CASE 369AA
STYLE 2
MARKING AND ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
September, 2011
−
Rev. 1
1
Publication Order Number:
NDD04N50Z/D
NDD04N50Z
THERMAL RESISTANCE
Parameter
Junction−to−Case (Drain)
Junction−to−Ambient Steady State
NDD04N50Z
(Note 3) NDD04N50Z
(Note 2) NDD04N50Z−1
Symbol
R
qJC
R
qJA
Value
2.0
40
80
Unit
°C/W
2. Insertion mounted
3. Surface mounted on FR4 board using 1″ sq. pad size, (Cu area = 1.127 in sq [2 oz] including traces).
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Breakdown Voltage Temperature Coeffi-
cient
Drain−to−Source Leakage Current
BV
DSS
DBV
DSS
/
DT
J
I
DSS
I
GSS
R
DS(on)
V
GS(th)
g
FS
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
V
GP
R
g
t
d(on)
t
r
t
d(off)
t
f
V
DD
= 250 V, I
D
= 3.4 A,
V
GS
= 10 V, R
G
= 5
W
1.8
V
DD
= 250 V, I
D
= 3.4 A,
V
GS
= 10 V
V
GS
= 0 V, I
D
= 1 mA
Reference to 25°C,
I
D
= 1 mA
V
DS
= 500 V, V
GS
= 0 V
V
GS
=
±20
V
V
GS
= 10 V, I
D
= 1.5 A
V
DS
= V
GS
, I
D
= 50
mA
V
DS
= 15 V, I
D
= 1.5 A
246
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
33
7.0
6.0
1.3
3.5
3.0
2.1
308
43
9.0
12
2.6
6.1
6.6
5.4
9.0
9.0
16
10
16.2
370
53
11
18
4.0
7.0
V
W
ns
nC
2.3
25°C
150°C
500
0.6
1.0
50
±10
2.7
4.5
mA
W
V
S
pF
V
V/°C
mA
Symbol
Test Conditions
Min
Typ
Max
Unit
Gate−to−Source Forward Leakage
ON CHARACTERISTICS
(Note 4)
Static Drain−to−Source
On−Resistance
Gate Threshold Voltage
Forward Transconductance
DYNAMIC CHARACTERISTICS
Input Capacitance (Note 5)
Output Capacitance (Note 5)
Reverse Transfer Capacitance (Note 5)
Total Gate Charge (Note 5)
Gate−to−Source Charge (Note 5)
Gate−to−Drain (“Miller”) Charge (Note 5)
Plateau Voltage
Gate Resistance
RESISTIVE SWITCHING CHARACTERISTICS
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
SOURCE−DRAIN DIODE CHARACTERISTICS
(T
C
= 25°C unless otherwise noted)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
4. Pulse Width
≤
380
ms,
Duty Cycle
≤
2%.
5. Guaranteed by design.
V
SD
t
rr
Q
rr
I
S
= 3.4 A, V
GS
= 0 V
V
GS
= 0 V, V
DD
= 30 V
I
S
= 3.4 A, di/dt = 100 A/ms
240
0.9
1.6
V
ns
mC
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2
NDD04N50Z
4.0
3.5
I
D
, DRAIN CURRENT (A)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
5.0 V
5.0
10.0
15.0
20.0
25.0
5.5 V
6.0 V
V
GS
= 10 V
7.0 V
6.5 V
I
D
, DRAIN CURRENT (A)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3
T
J
= 150°C
T
J
= 25°C
V
DS
= 25 V
T
J
=
−55°C
5
6
7
8
9
10
4
Figure 1. On−Region Characteristics
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 2. Transfer Characteristics
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2.25
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
I
D
= 1.5 A
T
J
= 25°C
4.00
3.75
V
GS
= 10 V
T
J
= 25°C
3.50
3.25
3.00
2.75
2.50
2.25
2.00
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
10.0
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
Figure 3. On−Region versus Gate−to−Source
Voltage
BV
DSS
, NORMALIZED BREAKDOWN VOLTAGE (V)
Figure 4. On−Resistance versus Drain
Current and Gate Voltage
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
−50
−25
0
25
50
75
100
125
I
D
= 1.5 A
V
GS
= 10 V
1.15
I
D
= 1 mA
1.10
1.05
1.00
0.95
0.90
−50
150
−25
0
25
50
75
100
125
150
T
J
, JUNCTION TEMPERATURE (°C)
T
J
, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. BV
DSS
Variation with Temperature
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3
NDD04N50Z
10.0
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
T
J
= 25°C
V
GS
= 0 V
f = 1 MHz
C
iss
C
oss
C
rss
1.0
T
J
= 150°C
T
J
= 125°C
0.1
0
50
100 150 200 250 300 350 400 450 500
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
I
DSS
, LEAKAGE (mA)
0.01
0.1
1
10
100
Figure 7. Drain−to−Source Leakage Current
versus Voltage
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 8. Capacitance Variation
10
V
DS
8
6
4
2
0
Q
GD
Q
T
V
GS
Q
GS
250
200
150
100
V
DS
= 250 V
I
D
= 3.4 A
T
J
= 25°C
0
1
2
3
4
5
6
7
8
9
10
11
50
0
12
Q
g
, TOTAL GATE CHARGE (nC)
Figure 9. Gate−to−Source Voltage and
Drain−to−Source Voltage versus Total Charge
1000
I
S
, SOURCE CURRENT (A)
V
DD
= 250 V
I
D
= 3.4 A
V
GS
= 10 V
100
t, TIME (ns)
t
d(off)
t
r
t
f
t
d(on)
10.0
1.0
T
J
= 150°C
10
125°C
25°C
−55°C
0.1
0.3
1
1
10
R
G
, GATE RESISTANCE (W)
100
0.4
0.5
0.6
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
0.7
0.8
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
12
300
0.9
1.0
1.1
1.2
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Resistive Switching Time Variation
versus Gate Resistance
Figure 11. Diode Forward Voltage versus
Current
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4
NDD04N50Z
100
V
GS
v
30 V
SINGLE PULSE
T
C
= 25°C
I
D
, DRAIN CURRENT (A)
10
100
ms
10
ms
1 ms
10 ms
dc
1
0.1
0.01
0.1
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
100
1000
Figure 12. Maximum Rated Forward Biased
Safe Operating Area NDD04N50Z
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
10
1
R(t) (C/W)
50% (DUTY CYCLE)
20%
10%
5.0%
0.1
2.0%
1.0%
SINGLE PULSE
R
qJA
= 2°C/W
Steady State
1E−04
1E−03
1E−02
1E−01
PULSE TIME (s)
1E+00
1E+01
1E+02
1E+03
0.01
1E−06
1E−05
Figure 13. Thermal Impedance (Junction−to−Case) for NDD04N50Z
100
R(t) (C/W)
10
50% (DUTY CYCLE)
20%
10%
1
5.0%
2.0%
1.0%
0.1
R
qJA
= 40°C/W
Steady State
1E−04
1E−03
1E−02
1E−01
1E+00
1E+01
1E+02
1E+03
0.01
1E−06
SINGLE PULSE
1E−05
PULSE TIME (s)
Figure 14. Thermal Impedance (Junction−to−Ambient) for NDD04N50Z
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