NCP5623
Triple Output I2C Controlled
RGB LED Driver
The NCP5623 mixed analog circuit is a triple output LED driver
dedicated to the RGB illumination or backlight LCD display.
Features
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MARKING
DIAGRAM
14
14
1
5623
A
L
Y
W
G
+5 V
TSSOP−14
CASE 948G
1
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
5623
ALYWG
G
•
•
•
•
•
•
•
•
•
•
•
2.7 to 5.5 V Input Voltage Range
RGB Function Fully Supported
Programmable Integrated Gradual Dimming
90 mA Total LED Current Capability
Provides Three Independent LED Drives
Support I2C Protocol
This is a Pb−Free Device
Multicolor Illuminations
Portable Back Light
Digital Cellular Phone Camera Photo Flash
LCD and Key Board Simultaneous Drive
+Vbat
+Vcc
1
mF/6.3
V
GND
MCU
SDA
SCL
I2C Port
GND
GND
62 k
C1
13
12
9
11
R1 10
6
2
U1
NCP5623
Vbat
Vdet
SDA
SCL
IREF
GND
GND
IC NC NC IC
1
7
8 14
LED3
LED2
LED1
5
4
3
6
2
5
C2
GND
1
mF/6.3
V
D1
R
G
B
1
3
4
Typical Applications
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
NCP5623DTBR2G
Package
TSSOP−14
(Pb−Free)
Shipping
†
2500 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
LRTB−G6T
Figure 1. Typical Multiple Color LED Driver
©
Semiconductor Components Industries, LLC, 2008
October, 2008
−
Rev. 6
1
Publication Order Number:
NCP5623/D
NCP5623
TSSOP−14
IC 1
GND 2
LED3 3
LED2 4
LED1 5
GND 6
NC 7
(Top View)
14 IC
13 Vbat
12 Vdet
11 SCL
10 IREF
9 SDA
8 NC
Figure 2. Pin Assignments
1
12
1
mF/6.3
V
C1
6
GND
SDA
SCL
9
11
Vbat
PWM LED#1
PWM LED#2
PWM LED#3
DIGITAL CONTROL
Vbat
13
IC
7
NC
8
NC
14
IC
+5 V
C2
1.0
mF/6.3
V
NCP5623
GND
GND
Vbat
LED3
3
GND
LED2
4
GND LED1
5
GND
CURRENT GND
MIRRORS
2
D3
D2
D1
R1
62 k
GND
10
ANALOG
FUNCTIONS
GND
Figure 3. Simplified Block Diagram
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2
NCP5623
PIN ASSIGNMENT
Pin
1
2
3
Name
IC
GND
LED3
POWER
OUTPUT,
POWER
OUTPUT,
POWER
OUTPUT,
POWER
ANALOG
GROUND
Type
Description
This pin is internally connected. It must be left open.
This pin is the GROUND signal for the analog and digital blocks and output current control. The
pin must be connected to the system ground, a ground plane being strongly recommended.
This pin sinks to ground and monitors the current flowing into the BLUE LED, intended to be
used in illumination application (Note 1). The Anode of the associated LED shall be connected
to the Vbat supply.
This pin sinks to ground and monitors the current flowing into the GREEN LED, intended to be
used in illumination application (Note 1). The Anode of the associated LED shall be connected
to the Vbat supply.
This pin sinks to ground and monitors the current flowing into the RED LED, intended to be
used in illumination application (Note 1). The anode of the associated LED shall be connected
to the Vbat supply.
This pin copies the Analog Ground and shall be connected to the system ground plane.
This pin must be left floating with no connection.
INPUT,
DIGITAL
ANALOG
This pin carries the data provided by the I2C protocol. The content of the SDA byte is used to
program the mode of operation and to set up the output current.
This pin provides the reference current, based on the internal band−gap voltage reference, to
control the output current flowing in the LED. A 1% tolerance, or better, resistor shall be used to
get the highest accuracy of the LED current. An external current mirror can be used to bias this
pin to dynamically set up the LED maximum current.
In no case shall the voltage at I
REF
pin be forced either higher or lower than the 600 mV
provided by the internal reference.
This pin carries the I2C clock to control the I2C communication. The SCL clock is associated
with the SDA signal.
This pin provides a DC bias to the internal circuit and must be connected to the same voltage
that the one applied to the Vbat pin 13.
This pin is the input Battery voltage to supply the analog and digital blocks. The pin must be
decoupled to ground by a 1
mF
or higher ceramic capacitor (Note 2).
This pin is internally connected. It must be left open.
4
LED2
5
LED1
6
7, 8
9
10
GND
NC
SDA
I
REF
11
12
13
14
SCL
Vdet
Vbat
IC
INPUT,
DIGITAL
INPUT
POWER
1. The maximum current is 37 mA for each LED
2. Using low ESR ceramic capacitor, X5R type, is recommended.
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NCP5623
MAXIMUM RATINGS
Symbol
V
bat
SDA, SCL
ESD
P
D
R
qJC
R
qJA
T
A
T
J
T
Jmax
T
stg
I
LATCHUP
Power Supply (see Figure 4)
Digital Input Voltage
Human Body Model: R = 1500
W,
C = 100 pF (Note 3)
Machine Model
Power Dissipation @ T
A
= +85°C (Note 4)
Thermal Resistance Junction to Case
Thermal Resistance Junction to Air
Operating Ambient Temperature Range
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Latch−up current maximum rating per JEDEC standard: JESD78.
Rating
Value
−0.3
< V
bat
< 7.0
−0.3
< V < V
bat
2
200
235
46
170
−40
to +85
−40
to +125
+150
−65
to +150
±100
Unit
V
V
kV
V
mW
°C/W
°C/W
°C
°C
°C
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM)
±2.0
kV per JEDEC standard: JESD22−A114
Machine Model (MM)
±200
V per JEDEC standard: JESD22−A115
4. The maximum package power dissipation limit must not be exceeded.
POWER SUPPLY SECTION:
(Typical values are referenced to T
A
= +25°C, Min & Max values are referenced
−40°C
to +85°C ambient temperature, unless otherwise
noted), operating conditions 2.85 V < V
bat
< 5.5 V, unless otherwise noted.
Pin
13
13
13
3,4,5
Symbol
V
bat
I
stdb
I
op
I
TOL
Power Supply
Stand By Current
3.0 V
≤
V
bat
≤
4.2 V, I
LED
= 0 mA
Operating Current,
@I
LED
= 0 mA, 3.0 V
≤
V
bat
≤
4.2 V
RGB Output Current Tolerance
@V
bat
= 3.6 V, I
LED
= 10 mA
−25°C
< T
A
< 85°C
RGB Output Current LED Matching
@V
bat
= 3.6 V, I
LED
= 5.0 mA
Internal Clock Operating Frequency
−40°C
< T
A
< 85°C
0.8
Rating
Min
2.7
0.8
350
±3
Typ
Max
5.5
1.0
Unit
V
mA
mA
%
3,4,5
I
MATCH
Fpwr
±0.5
1
1.2
%
MHz
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NCP5623
ANALOG SECTION:
(Typical values are referenced to T
A
= +25°C, Min & Max values are referenced
−40°C
to +85°C ambient temperature, unless otherwise
noted), operating conditions 2.85 V < V
bat
< 5.5 V, unless otherwise noted.
Pin
10
10
Symbol
I
REF
V
REF
I
LEDR
10
3,4,5
Rbias
F
PWM
Rating
Reference current @V
REF
= 600 mV
(Note 5, Note 8)
Reference Voltage (Note 5)
Reference Current (I
REF
) current ratio
External Reference current Bias resistor (Note 6)
Internal PWM Frequency (Note 7)
30
Min
3
−3%
Typ
12.5
600
2400
48
2.1
200
kW
kHz
Max
20
+3%
Unit
mA
mV
5. The external circuit must not force the I
REF
pin voltage either higher or lower than the 600 mV specified. The system is optimized with a
12.5
mA
reference current.
6. The overall output current tolerance depends upon the accuracy of the external resistor. Using 1% or better resistor is recommended.
7. This parameter, derived from the 1 MHz clock, is guaranteed by design, not tested in production.
DIGITAL PARAMETERS SECTION:
(Typical values are referenced to T
A
= +25°C, Min & Max values are referenced
−40°C
to +85°C ambient temperature, unless otherwise
noted), operating conditions 2.85 V < V
bat
< 5.5 V, unless otherwise noted.
Pin
11
9,11
9,11
Symbol
F
SCL
V
IH
V
IL
Rating
Input I2C clock frequency
Positive going Input High Voltage Threshold,
SDA, SCL signals (Note 8)
Negative going Input Low Voltage Threshold,
SDA, SCL signals (Note 8)
1.6
0
Min
Typ
Max
400
V
bat
0.4
Unit
kHz
V
V
NOTE: Digital inputs undershoot
≤
0.30 V to ground, Digital inputs overshoot < 0.30 V to V
bat
8. Test guaranteed by design and fully characterized, not implemented in production.
The chip might be damaged or destroyed
when Vbat is above 7.0 V
Absolute Maximum Rating
Maximum Voltage Operation
Chip functionnal, but no parameter guaranteed
when Vbat is between 5.5 V & 7.0 V
7.0 V
5.5 V
4.2 V
NORMAL Li−IonOPERATION
3.0 V
2.7 V
2.0 V
Power On Reset
No operation during POR
Reserved for internal Reset
Note: the internal POR sequence is 850
ms
maximum long
Figure 4. Understanding Integrated Circuit Voltage Limitations
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