NCP5378
Single Phase Synchronous
Buck Controller with
Integrated Gate Drivers and
Programmable DAC
The NCP5378 is a single chip solution which combines differential
voltage sensing, differential phase current sensing, adaptive voltage
positioning, and on board gate drivers to provide accurately regulated
power for Intel processors. This controller IC maintains the same
features as the multi−phase product family, but reduces the output to a
single−phase, for lower current systems. Low power mode operation
combined with inductor current sensing reduces system cost by
providing the fastest initial response to dynamic load events.
The gate drive adaptive non overlap and power saving operation
circuit can provide a low switching loss and high efficiency solution
for notebook and desktop systems. A high performance operational
error amplifier is provided to simplify compensation of the system.
Dynamic Reference Injection further simplifies loop compensation by
eliminating the need to compromise between closed−loop transient
response and Dynamic VID performance.
Features
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32
QFN32
CASE 488AM
MARKING DIAGRAM
1
NCP5378
AWLYYWWG
G
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Meets Intel’s VR11.1 Specifications
High Performance Operational Error Amplifier
Internal Soft Start
Dynamic Reference Injection (Patent #US07057381)
DAC Range from 0.5 V to 1.6 V
±0.5%
DAC Voltage Accuracy from 1.0 V to 1.6 V
True Differential Remote Voltage Sensing Amplifier
“Lossless” Differential Inductor Current Sensing
Adaptive Voltage Positioning (AVP)
Latched Over Voltage Protection (OVP)
Guaranteed Startup into Pre−Charged Loads
Threshold Sensitive Enable Pin for VTT Sensing
Power Good Output with Internal Delays
Thermally Compensated Current Monitoring
Thermal Shutdown Protection
Adaptive−Non−Overlap Gate Drive Circuit
Integrated MOSFET Drivers
Automatic Power−saving Modes Maximize Efficiency during Light
Load Operation
•
32−lead QFN
•
This is a Pb−Free Device
Applications
PIN CONNECTIONS
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VR_RDY
IMON
VSP
VSN
VFB
COMP
DIFFOUT
ILIM
1
QFN−32
(Top View)
VCC
BST
TG
SWN
VCCP
BG
EN
OFS
ORDERING INFORMATION
Device
NCP5378MNR2G
Package
QFN32
(Pb−Free)
Shipping
†
2500/Tape & Reel
•
Desktop Power Supplies for Next−generation Intel Chipsets
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NCP5378/D
©
Semiconductor Components Industries, LLC, 2009
October, 2009
−
Rev. 1
1
ROSC
VDRP
DAC
VDFB
CSSUM
CSN
CSP
12VMON
NCP5378
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
OFS
Flexible DAC
Overvoltage
Protection
UVLO
+
−
VCCP
−
+
BOOT
+
VSN
VSP
−
+
Diff Amp
−
Phase 1
Gate Driver
with
Adaptive
Non−overlap
TG
SWN
BG
DIFFOUT
1.3 V
+
VFB
−
Error Amp
COMP
VDRP
VDFB
CSSUM
CSP
CSN
+
−
−
Gain = 6
+
−
RPM
Threshold
ROSC
IMON
12VMON
+
ILIM
EN
VCC
+
−
4.25 V
UVLO
−
ILimit
Control,
Fault Logic
and
Monitor
Circuits
VR_RDY
GND (FLAG)
Figure 1. Functional Block Diagram
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2
NCP5378
Table 1. PIN DESCRIPTIONS
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33/
FLAG
Symbol
VR_RDY
IMON
VSP
VSN
VFB
COMP
DIFFOUT
ILIM
ROSC
VDRP
DAC
VDFB
CSSUM
CSN
CSP
12VMON
OFS
EN
BG
VCCP
SWN
TG
BST
VCC
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
GND
Description
Open collector output. High indicates that the output is regulating
0 to 1 Volt analog signal proportional to the output load current. VSN referenced Clamped to 1.1 Vmax
Non−inverting input to the internal differential remote sense amplifier
Inverting input to the internal differential remote sense amplifier
Compensation amplifier voltage feedback
Output of the compensation amplifier
Output of the differential remote sense amplifier
Over current shutdown threshold setting. ILIM = VDRP – 1.3 V. Resistor divide ROSC to set threshold
A resistance from this pin to ground programs the oscillator frequency according to f SW = 1 / (ROSC
•
100 pF). This pin supplies a trimmed output voltage of 2.00 V.
Voltage output signal proportional to current used for current limit and output voltage droop
DAC output used to provide feed forward for dynamic VID
Droop Amplifier Voltage Feedback
Inverted Sum of the Differential Current Sense inputs.
Inverting input to current sense amplifier
Non−inverting input to current sense amplifier
Monitor a 12 V input through a resistor divider
External Offset
Threshold sensitive input. High = startup, Low = shutdown.
Low side gate drive
Power VCC for gate drivers with UVLO monitor
Switch Node
High side gate drive
Upper MOSFET floating BSTstrap supply for driver
Power for the internal control circuits with UVLO monitor
Voltage ID DAC input
Voltage ID DAC input
Voltage ID DAC input
Voltage ID DAC input
Voltage ID DAC input
Voltage ID DAC input
Voltage ID DAC input
Voltage ID DAC input
Power supply return (QFN Flag)
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NCP5378
ABSOLUTE MAXIMUM RATINGS
Rating
ELECTRICAL INFORMATION
Controller Power Supply Voltages to GND
Driver Power Supply Voltages to GND
High−Side Gate Driver Supplies: BST to SWN
V
CC
V
CCP
V
BST
−
V
SWN
−0.3,
7
−0.3,
15
40 V wrt/GND
40 V
≤
50 ns wrt/GND
−0.3,
15 wrt/SWN
BOOT + 0.3 V
35 V
≤
50 ns wrt/GND
−0.3,
15 wrt/SWN
−5
V (200 ns)
35
40 V
≤
50 ns wrt/GND
−5
VDC
−10
V (200 ns)
V
CC
+ 0.3 V
−5
V (200 ns)
−0.3,
6
0
GND
±300
V
IMON
1.1
−0.3,
5.5
V
V
V
Symbol
Value
Unit
High−Side FET Gate Driver Voltages: TG to SWN
V
TG
−
V
SWN
V
Switch Node: SWN
V
SWN
V
Low−Side Gate Drive: BG
Logic Inputs
GND
V−
Imon Out
All Other Pins
THERMAL INFORMATION
Thermal Characteristic
QFN Package (Note 1)
Operating Junction Temperature Range (Note 2)
Operating Ambient Temperature Range
Maximum Storage Temperature Range
Moisture Sensitivity Level
QFN Package
V
BG
−
AGND
V
LOGIC
V
GND
V
V
V
mV
V
V
R
qJA
T
J
T
AMB
T
STG
MSL
32.6
0 to 125
0 to +70
−55
to +150
1
°C/W
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*All signals referenced to GND unless noted otherwise.
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. Operation at
−40°C
to 0°C guaranteed by design, not production tested.
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NCP5378
ELECTRICAL CHARACTERISTICS
0°C < T
A
< 70°C; 0°C < T
J
< 125°C; 4.75 < V
CC
< 5.25 V; All DAC Codes; C
VCC
= 0.1
mF
unless otherwise noted.
Parameter
ERROR AMPLIFIER
Input Bias Current
Open Loop DC Gain
Open Loop Unity Gain Bandwidth
Open Loop Phase Margin
Slew Rate
C
L
= 60 pF to GND,
R
L
= 10 kW to GND
C
L
= 60 pF to GND,
R
L
= 10 kW to GND
C
L
= 60 pF to GND,
R
L
= 10 kW to GND
DV
in
= 100 mV, G =
−10V/V,
DV
out
= 1.5 V
−
2.5 V,
C
L
= 60 pF to GND,
DC Load =
±125
mA
to GND
10 mV of Overdrive,
I
SOURCE
= 2.0 mA
10 mV of Overdrive,
I
SINK
= 500
mA
10 mV of Overdrive,
V
out
= 3.5 V
10 mV of Overdrive,
V
out
= 0.1 V
DRVON = low
DRVON = high
DRVON = low
DRVON = high
−200
−
−
−
−
−
100
18
70
10
200
−
−
−
−
nA
dB
MHz
°
V/ms
Test Conditions
Min
Typ
Max
Unit
Maximum Output Voltage
Minimum Output Voltage
Output Source Current
Output Sink Current
DIFFERENTIAL SUMMING AMPLIFIER
V+ Input Pull down Resistance
V+ Input Bias Voltage
Input Voltage Range (Note 3)
−3
dB Bandwidth
Closed Loop DC gain VS to Diffout (Note 3)
Maximum Output Voltage
Minimum Output Voltage
Output Source Current
Output Sink Current
INTERNAL OFFSET VOLTAGE
Offset Voltage to the (+) Pin of the Error Amp &
the VDRP Pin
VDROOP AMPLIFIER
Input Bias Current
Inverting Voltage Range
Open Loop DC Gain
Open Loop Unity Gain Bandwidth
3.0
−
1.5
0.65
−
−
2.0
1.0
−
75
−
−
V
mV
mA
mA
−
−
−
0.8
−0.3
0.6
6.0
0.05
0.88
−
15
1.0
−
−
2.0
1.5
−
−
0.1
0.95
3.0
−
1.02
−
0.5
−
−
kW
V
V
MHz
V/V
V
V
mA
mA
C
L
= 80 pF to GND,
R
L
= 10 kW to GND
VS+ to VS− = 0.5 V to 1.6 V
10 mV of Overdrive,
I
SOURCE
= 2 mA
10 mV of Overdrive,
I
SINK
= 1 mA
10 mV of Overdrive,
V
out
= 3 V
10 mV of Overdrive,
V
out
= 0.2 V
−
0.98
3.0
−
1.5
1.0
−2
0
+2
mV
−200
0
C
L
= 20 pF to GND including ESD
R
L
= 1 kW to GND
C
L
= 20 pF to GND including ESD
R
L
= 1 kW to GND
−
−
−
1.3
100
18
200
3.0
−
−
nA
V
dB
MHz
3. Guaranteed by design.
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
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