3.3V ATM PHY
for 25.6 and 51.2 Mbps
IDT77V106L25
FEATURES:
•
Performs the PHY-Transmission Convergence (TC) and
DESCRIPTION:
The IDT77V106L25 is a member of IDT’s family of products supporting
Asynchronous Transfer Mode (ATM) data communications and networking.
The IDT77V106L25 implements the physical layer for 25.6 Mbps ATM,
connecting a serial copper link (UTP Category 3 and 5) to an ATM layer device
such as a SAR or a switch ASIC. The IDT77V106L25 also operates at 51.2
Mbps and is well suited to back-plane driving applications. The 77V106L25
utilizes an 8-bit UTOPIA interface on the cell side.
The IDT77V106L25 is fabricated using IDT’s state-of-the-art CMOS
technology, providing the highest levels of integration, performance and
reliability, with the low-power consumption characteristics of CMOS.
Physical Media Dependent (PMD) Sublayer functions of the
Physical Layer
•
Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
specifications for 25.6Mbps physical interface
•
Also operates at 51.2Mbps data rate
•
8-bit UTOPIA Level 1 Interface
•
3-Cell Transmit & Receive FIFOs
•
Receiver Auto-Synchronization and Good Signal Indication
•
LED Interface for status signalling
•
Supports UTP Category 3 and 5 physical media
•
Interfaces to standard magnetics
•
Low-Power CMOS
•
3.3V supply with 5V tolerant inputs
•
64-lead TQFP Package (10 x 10 mm)
•
Commercial and Industrial Temperature Ranges
APPLICATIONS:
•
Up
to 51.2Mbps backplane transmission
•
Rack-to-rack short links
•
ATM Switches
BLOCK DIAGRAM
TXLED
TXREF
TXCLK
TXDATA 9
TXSOC
TXEN
TXCLAV
3 CELL FIFO
SCRAMBLER
4B/5B
ENCODER
P/S
NRZI
Line
Driver
TXD+
TXD-
PRNG
ALE
WR
RD
CS
AD[7:0]
INT
RESET
8
UTILITY
BUS
CONTROLLER
RESET
LOOP BACK
RXCLK
RXDATA
RXSOC
RXEN
RXCLAV
RXREF
Line
RXVR
9
3 CELL FIFO
DESCRAMBLER
5B/4B
DECODER
S/P
DNRZI
CLK
REC
RXD+
RXD-
77V106
OSC
RxLED
77v106 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
JULY 2003
1
DSC-5360/3
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice
IDT77V106L25
77V106L25 OVERVIEW
The 77V106L25 is a physical layer interface chip for 25.6Mbps ATM
network communications as defined by ATM Forum document af-phy-040.000
and ITU-T I.432.5. The physical layer is divided into a Physical Media
Dependent sub layer (PMD) and Transmission Convergence (TC) sub layer.
The PMD sub layer includes the functions for the transmitter, receiver and clock
recovery for operation across 100 meters of category 3 and 5 unshielded
twisted pair (UTP) cable. This is referred to as the Line Side Interface. The TC
sub layer defines the line coding, scrambling, data framing and synchronization.
On the cell side, the 77V106L25 connects to an ATM layer device (such
as a switch core or SAR) through an 8-bit Utopia Level 1 interface.
The 77V106L25 is based on the 77105 and maintains significant register
compatibility with it, but it also has additional register features.
Access to these status and control registers is through the utility bus. This
is an 8-bit muxed address and data bus, controlled by a conventional
asynchronous read/write handshake.
Additional pins permit insertion and extraction of an 8kHz timing marker,
and provide LED indication of receive and transmit status.
OPERATION AT 51.2 Mbps
In addition to operation at the standard rate of 25.6 Mbps, the 77V106L25
is also specified to operate at 51.2 Mbps. Except for the doubled bit rate, all other
aspects of operation are identical to the 25.6 Mbps mode.
The rate is determined by the frequency of the clock applied to the OSC
input pin. OSC is 32 MHz for the 25.6 Mbps line rate, and 64 MHz for the 51.2
Mbps line rate.
See Figure 16 for recommended line magnetics. Magnetics for 51.2 Mbps
operation have a higher bandwidth than magnetics optimized for 25.6 Mbps.
RXREF
TXREF
TXLED
TXDATA0
TXDATA1
TXDATA2
TXDATA3
TXDATA4
TXDATA5
TXDATA6
TXDATA7
TXPARITY
TXEN
TXSOC
VDD
TXCLAV
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
Pin 1 Index
4
45
5
44
6
43
7
42
8
41
IDT77V106
9
40
10
39
11
38
12
37
36
13
14
35
34
15
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RXEN
RXCLAV
RXSOC
GND
RXPARITY
RXDATA7
RXDATA6
RXDATA5
RXDATA4
VDD
RXDATA3
RXDATA2
RXDATA1
RXDATA0
TXCLK
RXCLK
SM
VDD
TXD+
TXD-
GND
AVDD
RXD+
RXD-
AVDD
AGND
AVDD
AGND
OSC
AVDD
AGND
SE
AD7
AD6
AD5
AD4
GND
AD3
AD2
AD1
AD0
ALE
CS
RD
WR
RST
INT
RXLED
77v106 drw 02
77v106 drw 02
Figure 1. Pin Assignments
2
IDT77V106L25
TABLE 1 — SIGNAL DESCRIPTION (PART 1 OF 2)
Line Side Signals
Signal Name
RXD+, RXD-
TXD+, TXD-
Signal Name
AD[7:0]
Pin Number
58, 57
62, 61
Pin Number
48, 47, 46,
45, 43, 42,
41, 40.
39
38
37
36
I/O
In
Out
I/O
In/
Out
In
In
In
In
Signal Description
Positive and negative receive differential input pair.
Positive and negative transmit differential output pair.
Utility Bus Signals
Signal Description
Utility bus address/data bus. The address input is sampled on the falling edge of ALE. Data is output on this
bus when a read is performed. Input data is sampled at the completion of a write operation.
Utility bus address latch enable. Asynchronous input. An address on the AD bus is sampled on the falling
edge of ALE. ALE must be low when the AD bus is being used for data.
Utility bus asynchronous chip select.
CS
must be asserted to read or write an internal register. It may remain
asserted at all times if desired.
Utility bus read enable. Active low asynchronous input. After latching an address, a read is performed by
deasserting
WR
and asserting
RD
and
CS.
Utility bus write enable. Active low asynchronous input. After latching an address, a write is performed by
deasserting
RD,
placing data on the
AD
bus, and asserting
WR
and
CS.
Data is sampled when
WR
or
CS
is deasserted.
Utopia Bus Signals
Signal Name
RXCLAV
RXCLK
RXDATA[7:0]
Pin Number
20
18
24, 25, 26,
27, 29, 30
31, 32.
19
23
21
16
17
11, 10, 9, 8
7, 6, 5, 4
13
12
I/O
Out
In
Out
Signal Description
Utopia Receive Cell Available. "1" indicates that the receive FIFO contains a complete cell. "0" indicates that
it does not.
Utopia Receive Clock. This is a free running clock input.
Utopia Receive Data. When one of the four ports is selected, the 77V106L25 transfers received cells to an
ATM device across the bus. Also see RXPARITY.
Utopia Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA
bus.
Utopia Receive Data Parity. Odd parity over RXDATA[7:0].
Utopia Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA.
Utopia Transmit Cell Available. "1" indicates that the transmit FIFO has room available for at least one complete
cell. "0" indicates that it does not.
Utopia Transmit Clock. This is a free running clock input.
Utopia Transmit Data. An ATM device transfer cell across this bus to the 77V106L25 for transmission. Also
see TXPARITY.
Utopia Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA bus.
Utopia Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is checked and errors are indicated
in the Interrupt Status Registers, as enabled in the Master Control Register. No other action is taken in the
even of an error. Tie high or low if unused.
Utopia Transmit Start of Cell. Asserted coincident with the first word the first word of data for each cell on
TXDATA.
ALE
CS
RD
WR
RXEN
RXPARITY
RXSOC
TXCLAV
TXCLK
TXDATA[7:0]
TXEN
TXPARITY
In
Out
Out
Out
In
In
In
In
TXSOC
14
In
3
IDT77V106L25
TABLE 1 — SIGNAL DESCRIPTION (PART 2 OF 2)
Miscellaneous Signals
Signal Name
INT
Pin Number
34
I/O
Out
Signal Description
Interrupt
INT
is an open-drain output, driven low to indicate an interrupt. Once low,
INT
remains low until
the interrupt status in the appropriate interrupt Status Register is read. Interrupt sources are programmable
via the interrupt Mast Registers.
TTL line rate clock source, driven by a 100 ppm oscillator. 32MHz for 25.63 Mbps; 65 MHz for 51.2 Mbps.
Reset. Active low asynchronous input resets all control logic, counters and FIFOs. A reset must be performed
after power up prior to normal operation of the part.
Receive LED driver. Driven low for 223 cycles of OSC, beginning with RXSOC when a good (non-null and
non-errored) cell is received. Drives 8 mA both high and low.
Receive Reference. Active low.
RXREF
pulses low for a programmable number of clock cycles when an
X_8 command byte is received.
Reserved signal. This input must be connected to logic low.
Reserved signal. This input must be connected to logic low.
Transmit LED driver. Goes low for 223 cycles of OSC, beginning with TXSOC when a cell is received for
transmission. 8 mA drive current both high and low.
Transmit Reference. At the falling edge of
TXREF,
an X_8 command byte is inserted into the transmit data
stream. Typical application is WAN timing.
Power Supply Signals
Signal Name
AGND
AVDO
GND
VDD
Pin Number
50, 53, 55
51, 54, 56
59
22, 44, 60
15, 28,63
I/O
—
—
—
—
Signal Description
Analog ground. AGND is ground the analog portion of the ship, which sources a more constant current than
the digital portion.
Analog power supply. AVDO supplies power to the analog portion of the chip, which draws a more constant
current than the digital portion. 3.3
±
0.34V
Digital Ground.
Digital power supply. 3.3
±
0.3V
OSC
RST
RXLED
RXREF
SE
SM
TXLED
TXREF
52
35
33
1
49
64
3
2
In
In
Out
Out
In
In
Out
In
4
IDT77V106L25
Functional Description
Transmission Convergence (TC) Sub Layer
Introduction
The TC sub layer defines the line coding, scrambling, data framing and
synchronization. Under control of a switch interface or Segmentation and
Reassembly (SAR) unit, the 25.6Mbps ATM PHY accepts a 53-byte ATM cell,
scrambles the data, appends a command byte to the beginning of the cell, and
encodes the entire 53 bytes before transmission. These data transformations
ensure that the signal is evenly distributed across the frequency spectrum. In
addition, the serialized bit stream is NRZI coded. An 8kHz timing sync pulse
may be used for isochronous communications.
Data Structure and Framing
Each 53-byte ATM cell is preceded with a command byte. This byte is
distinguished by an escape symbol followed by one of 17 encoded symbols.
Together, this byte forms one of seventeen possible command bytes. Three
command bytes are defined:
1.
X_X
(read: ‘escape’ symbol followed by another ‘escape’): Start-of-
cell with scrambler/descrambler reset.
2.
X_4
(‘escape’ followed by ‘4’): Start-of-cell without scrambler/
descrambler reset.
3.
X_8
(‘escape’ followed by ‘8’): 8kHz timing marker. This command
byte is generated when the 8kHz sync pulse is detected, and has
priority over all line activity (data or command bytes). It is transmitted
immediately when the sync pulse is detected. When this occurs
during a cell transmission, the data transfer is temporarily interrupted
on an octet boundary, and the X_8 command byte is inserted. This
condition is the only allowed interrupt in an otherwise contiguous
transfer.
Below is an illustration of the cell structure and command byte usage:
{X_X} {53-byte ATM cell} {X_4} {53-byte ATM {X_8} cell}...
In the above example, the first ATM cell is preceded by the X_X start-of-
cell command byte which resets both the transmitter-scrambler and receiver-
descrambler pseudo-random nibble generators (PRNG) to their initial states.
The following cell illustrates the insertion of a start-of-cell command without
scrambler/descrambler reset. During this cell’s transmission, an 8kHz timing
sync pulse triggers insertion of the X_8 8kHz timing marker command byte.
Transmission Description
Refer to Figure 2. Cell transmission begins with the PHY-ATM Interface.
An ATM layer device transfers a cell into the 77V106L25 across the Utopia
transmit bus. This cell enters a 3-cell deep transmit FIFO. Once a complete cell
is in the FIFO, transmission begins by passing the cell, four bits (MSB first) at
a time to the ‘Scrambler’.
The ‘Scrambler’ takes each nibble of data and exclusive-ORs them against
the 4 high order bits (X(t), X(t-1), X(t-3)) of a 10 bit pseudo-random nibble
generator (PRING). Its function is to provide the appropriate frequency
distribution for the signal across the line.
The PRNG is clocked every time a nibble is processed, regardless of
whether the processed nibble is part of a data or command byte. Note however
that only data nibbles are scrambled. The entire command byte (X _C) is NOT
scrambled before it’s encoded (see diagram for
illustration).
The PRNG is based upon the following polynomial:
X
10
+ X
7
+ 1
With this polynomial, the four output data bits (D3, D2, D1, D0) will be
generated from the following equations:
D3 = d3 xor X(t-3)
D2 = d2 xor X(t-2)
D1 = d1 xor X(t-1)
D0 = d0 xor X(t)
The following nibble is scrambled with X(t+4), X(t+3), X(t+2), and X(t+1).
A scrambler lock between the transmitter and receiver occurs each time
an X_X command is sent. An X_X command is initiated only at the beginning
of a cell transfer after the PRNG has cycled through all of its states (2 - 1 = 1023
states). The first valid ATM data cell transmitted after power on will also be
accompanied with an X_X command byte. Each time an X_X command byte
is sent, the first nibble after the last escape (X) nibble is XOR’d with 1111b
(PRNG = 3FFx).
Because a timing marker command (X_8) may occur at any time, the
possibility of a reset PRNG start-of-cell command and a timing marker command
occurring consecutively does exist (e.g. X_X_X_8). In this case, the detection
of the last two consecutive escape (X) nibbles will cause the PRNG to reset to
its initial 3FFx state. Therefore, the PRNG is clocked only after the first nibble
of the second consecutive escape pair.
Once the data nibbles have been scrambled using the PRNG, the nibbles
are further encoded using a 4b/5b process. The 4b/5b scheme ensures that
an appropriate number of signal transitions occur on the line. A total of
seventeen 5-bit symbols are used to represent the sixteen 4-bit data nibbles
and the one escape (X) nibble. The table below lists the 4-bit data with their
corresponding 5-bit symbols:
10
Data
0000
0100
1000
1100
Symbol
10101
00111
10010
10111
Data
0001
0101
1001
1101
Symbol
01001
01101
11001
11101
Data
0010
0110
1010
1110
Symbol
01010
01110
11010
11110
Data
0011
0111
1011
1111
Symbol
01011
01111
11011
11111
3505 drw 05a
ESC(X) = 00010
5
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