BiCMOS SyncBiFIFO™
64 x 36 x 2
IDT723612
Integrated Device Technology, Inc.
FEATURES:
• Free-running CLKA and CLKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Two independent clocked FIFOs (64 x 36 storage
capacity each) buffering data in opposite directions
• Mailbox bypass Register for each FIFO
• Programmable Almost-Full and Almost-Empty Flags
• Microprocessor interface control logic
•
EFA
,
FFA
,
AEA
, and
AFA
flags synchronized by CLKA
•
EFB
,
FFB
,
AEB
, and
AFB
flags synchronized by CLKB
• Passive parity checking on each port
• Parity generation can be selected for each port
•
•
•
•
Low-power advanced BiCMOS technology
Supports clock frequencies up to 67 MHz
Fast access times of 10ns
Available in 132-pin plastic quad flat package (PQF) or
space-saving 120-pin thin quad flat package (TQFP)
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT723612 is a monolithic high-speed, low-power
BiCMOS bi-directional clocked FIFO memory. It supports
clock frequencies up to 67 MHz and has read access times as
FUNCTIONAL BLOCK DIAGRAM
CLKA
W/
R
A
ENA
MBA
CSA
Port-A
Control
Logic
Mail 1
Register
Parity
Gen/Check
MBF1
PEFB
PGB
Parity
Generation
Input
Register
RST
EVEN
ODD/
64 x 36
SRAM
Output
Register
36
Device
Control
Write
Pointer
Read
Pointer
FFA
AFA
FS0
FS1
A
0
- A
35
Status Flag
Logic
36
FIFO1
Programmable Flag
Offset Register
FIFO2
Status Flag
Logic
Read
Pointer
Parity
Generation
EFB
AEB
B
0
- B
36
EFA
AEA
FFB
AFB
36
Write
Pointer
Output
Register
64 x 36
SRAM
PGA
Parity
Gen/Check
Mail 2
Register
CLKB
PEFA
MBF2
Input
Register
Port-B
Control
Logic
CSB
W/
R
B
ENB
MBB
3136 drw 01
The IDT logo is a registered trademark and Sync BiFIFO is a trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
©1997
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
DSC-3136/4
1
IDT723612 BiCMOS SyncBiFIFO™
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
fast as 10ns. Two independent 64 x 36 dual-port SRAM
FIFOs on board the chip buffer data in opposite directions.
Each FIFO has flags to indicate empty and full conditions and
two programmable flags (almost-full and almost-empty) to
indicate when a selected number of words is stored in
memory. Communication between each port can bypass the
FIFOs via two 36-bit mailbox registers. Each mailbox register
has a flag to signal when new mail has been stored. Parity is
checked passively on each port and may be ignored if not
desired. Parity generation can be selected for data read from
each port. Two or more devices can be used in parallel to
create wider data paths.
The IDT723612 is a clocked FIFO, which means each port
employs a synchronous interface. All data transfers through
a port are gated to the LOW-to-HIGH transition of a port clock
by enable signals. The clocks for each port are independent
of one another and can be asynchronous or coincident. The
enables for each port are arranged to provide a simple bi-
directional interface between microprocessors and/or buses
with synchronous control.
The full flag (
FFA
,
FFB
) and almost-full (
AFA
,
AFB
) flag of
a FIFO are two-stage synchronized to the port clock that writes
data to its array. The empty flag (
EFA
,
EFB
) and almost-empty
(
AEA
,
AEB
) flag of a FIFO are two stage synchronized to the
port clock that reads data from its array.
The IDT723612 is characterized for operation from 0°C to
70°C.
PIN CONFIGURATIONS
ENA
CLKA
W/ A
V
CC
PGA
GND
A
0
A
1
A
2
GND
A
3
A
4
A
5
A
6
V
CC
A
7
A
8
A
9
GND
A
10
A
11
V
CC
A
12
A
13
A
14
GND
A
15
A
16
A
17
A
18
A
19
A
20
GND
A
21
A
22
A
23
V
CC
A
24
A
25
A
26
GND
A
27
A
28
A
29
V
CC
A
30
A
31
A
32
GND
A
33
A
34
A
35
GND
B
35
B
34
B
33
GND
B
32
B
31
B
30
V
CC
B
29
B
28
B
27
GND
B
26
B
25
B
24
V
CC
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
PGB
V
CC
W/ B
CLKB
ENB
MBA
FS
1
FS
0
ODD/
GND
GND
NC
NC
NC
NC
MBB
GND
*
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
GND
B
0
B
1
B
2
GND
B
3
B
4
B
5
B
6
V
CC
B
7
B
8
B
9
GND
B
10
B
11
V
CC
B
12
B
13
B
14
GND
B
15
B
16
B
17
B
18
B
19
B
20
GND
B
21
B
22
B
23
*
3136 drw 02
Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PQFP (PQ132-1, order code: PQF)
TOP VIEW
Note:
1. NC - No internal connection
2. Uses Yamaichi socket IC51-1324-828
2
IDT723612 BiCMOS SyncBiFIFO™
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONT.)
A
24
A
25
A
26
V
CC
A
27
A
28
A
29
GND
A
30
A
31
A
32
A
33
A
34
A
35
GND
B
35
B
34
B
33
B
32
B
31
B
30
GND
B
29
B
28
B
27
V
CC
B
26
B
25
B
24
B
23
A
23
A
22
A
21
GND
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
GND
A
9
A
8
A
7
V
CC
A
6
A
5
A
4
A
3
GND
A
2
A
1
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B
22
B
21
GND
B
20
B
19
B
18
B
17
B
16
B
15
B
14
B
13
B
12
B
11
B
10
GND
B
9
B
8
B
7
V
CC
B
6
B
5
B
4
B
3
GND
B
2
B
1
B
0
ENA
CLKA
W/ A
V
CC
PGA
GND
NC
NC
NC
NC
MBB
ODD/
PGB
V
CC
W/ B
CLKB
ENB
MBA
FS
1
FS
0
3136 drw 03
TQFP (PN120-1, order code: PF)
TOP VIEW
Note:
1. NC - No internal connection
3
IDT723612 BiCMOS SyncBiFIFO™
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
A0-A35
Name
Port-A Data
Almost-Empty Flag
I/O
I/O
O
(Port A)
Description
36-bit bidirectional data port for side A.
Programmable almost-empty flag synchronized to CLKA. It is LOW when
the number of words in the FIFO2 is less than or equal to the value in the
offset register, X.
Programmable almost-full flag synchronized to CLKB. It is LOW when the
number of words in FIFO1 is less than or equal to the value in the
offset register, X.
Programmable almost-full flag synchronized to CLKA. It is LOW when the
number of empty locations in FIFO1 is less than or equal to the value in the
offset register, X.
Programmable almost-full flag synchronized to CLKB. It is LOW when the
number of empty locations in FIFO2 is less than or equal to the value in the
offset register, X.
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through port-
A and can be aynchronous or coincident to CLKB.
EFA
,
FFA
,
AFA
, and
AEA
are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port-
B and can be asynchronous or coincident to CLKA.
EFB
,
FFB
,
AFB
, and
AEB
are synchronized to the LOW-to-HIGH transition of CLKB.
CSA
must be LOW to enable a LOW-to-HIGH transition of CLKA to read or
write data on port-A. The A0-A35 outputs are in the high-impedance state
when
CSA
is HIGH.
AEA
AEB
Port-B Almost-Empty
O
Flag
(PortB)
Port-A Almost-Full
Flag
O
(Port A)
AFA
AFB
B0-B35
CLKA
Port-B Almost-Empty
O
Flag
(Port B)
Port-B Data.
Port-A Clock
I/O
I
CLKB
Port-B Clock
I
CSA
CSB
EFA
Port-A Chip Select
I
Port-B Chip Select
I
B
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or
Port-A Empty Flag
O
(Port A)
EFB
Port-B Empty Flag
O
(Port B)
ENA
ENB
Port-A Enable
Port-B Enable
Port-A Full Flag
I
I
O
(Port A)
EFA
is synchronized to the LOW-to-HIGH transition of CLKA. When
EFA
is
LOW, FIFO2 is empty, and reads from its memory are disabled. Data can
be read from FIFO2 to the output register when
EFA
is HIGH.
EFA
is forced
LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKA after data is loaded into empty FIFO2 memory.
EFB
is synchronized to the LOW-to-HIGH transition of CLKB. When
EFB
is
LOW, the FIFO1 is empty, and reads from its memory are disabled. Data
can be read from FIFO1 to the output register when
EFB
is HIGH.
EFB
is
forced LOW when the device is reset and is set HIGH by the second LOW-
to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or
write data on port-A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or
write data on port-B.
FFA
is synchronized to the LOW-to-HIGH transition of CLKA. When
FFA
is
LOW, FIFO1 is full, and writes to its memory are disabled.
FFA
is forced
LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKA after reset.
LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKB after reset.
The LOW-to-HIGH transition of
RST
latches the values of FS0 and FS1,
which selects one of four preset values for the almost-full flag and almost-
empty flag.
A HIGH level on MBA chooses a mailbox register for a port-A read or write
operation. When the A0-A35 outputs are active, a HIGH level on MBA
selects data from the mail2 register for output, and a LOW level selects
FIFO2 output register data for output.
4
write data on port-B. The B0-B35 outputs are in the high-impedance state
when
CSB
is HIGH.
FFA
FFB
Port-B Full Flag
O
(Port B)
FFB
is synchronized to the LOW-to-HIGH transition of CLKB. When
FFB
is
LOW, FIFO2 is full, and writes to its memory are disabled.
FFB
is forced
FS1, FS0 Flag-Offset Selects
I
MBA
Port-A Mailbox Select
I
IDT723612 BiCMOS SyncBiFIFO™
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
SYMBOL
NAME
I/O
DESCRIPTION
MBB
Port-B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a port-B read or write
operation. When the B0-B35 outputs are active, a HIGH level on MBB selects
data from the mail1 register for output, and a LOW level selects FIFO1
output register data for output.
MBF1
Mail1 Register Flag
O
reset.
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data to
the mail1 register. Writes to the mail1 register are inhibited while
MBF1
is set
LOW.
MBF1
is set HIGH by a LOW-to-HIGH transition of CLKB when a port-
B read is selected and MBB is HIGH.
MBF1
is set HIGH when the device is
MBF2
Mail2 Register Flag
O
EVEN
PEFA
ODD/
Odd/Even Parity
Select
Port-A Parity Error
Flag
PEFB
Port-B Parity Error
Flag
PGA
Port-A Parity
reset.
I
Odd parity is checked on each port when ODD/
EVEN
is HIGH, and even
parity is checked when ODD/
EVEN
is LOW. ODD/
EVEN
also selects the
type of parity generated for each port if parity generation is enabled for a read
operation.
O
When any byte applied to terminals A0-A35 fails parity,
PEFA
is LOW.
(Port A) Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the
most significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/
EVEN
input. The parity trees
used to check the A0-A35 inputs are shared by the mail2 register to generate
parity if parity generation is selected by PGA. Therefore, if a mail2 read with
parity generation is setup by having W/
R
A LOW, MBA HIGH, and PGA HIGH,
the
PEFA
flag is forcedHIGH regardless of the A0-A35 inputs.
O
When any byte applied to terminals B0-B35 fails parity,
PEFB
is LOW.
(Port B) Bytes are organized as B0-B8, B9-B17, B18-B26, B27-B35 with the most
significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/
EVEN
input. The parity trees
used to check the B0-B35 inputs are shared by the mail1 register to generate
parity if parity generation is selected by PGB. Therefore, if a mail1 read with
parity generation is setup by having W/
R
B LOW, MBB HIGH, and PGB HIGH,
the
PEFB
flag is forced HIGH regardless of the state of the B0-B35 inputs.
I
Parity is generated for data reads from port A when PGA is HIGH. Genera-
tion The type of parity generated is selected by the state of the ODD/
EVEN
input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The
generated parity bits are output in the most significant bit of each byte.
I
Parity is generated for data reads from port B when PGB s HIGH. The type of
parity generated is selected by the state of the ODD/
EVEN
input. Bytes are
organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity
bits are output in the most significant bit of each byte.
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while
RST
is LOW. This sets the
AFA
,
AFB
,
MBF1
, and
MBF2
flags HIGH and the
EFA
,
EFB
,
AEA
,
AEB
,
FFA,
and
FFB
flags LOW. The LOW-to-HIGH transition of
RST
latches the status of the
FS1 and FS0 inouts to select almost-full and almost-empty flag offset.
A HIGH selects a write operation and a LOW selects a read operation on
port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the
high-impedance state when W/
R
A is HIGH.
A HIGH selects a write operation and a LOW selects a read operation on
port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the
high-impedance state when W/
R
B is HIGH.
MBF2
is set LOW by a LOW-to-HIGH transition of CLKB that writes data to
the mail2 register. Writes to the mail2 register are inhibited while
MBF2
is set
LOW.
MBF2
is set HIGH by a LOW-to-HIGH transition of CLKA when a port-
A read is selected and MBA is HIGH.
MBF2
is set HIGH when the device is
PGB
Port-B Parity
Generation
RST
Reset
I
W/
R
A
W/
R
B
Port-A Write/Read
Select
Port-B Write/Read
Select
I
I
5
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