NBVSBAXXX Series
2.5 V/3.3 V, LVPECL
Voltage-Controlled Crystal
Oscillator (VCXO)
PureEdget Product Series
The NBVSBAXXX series voltage−controlled crystal oscillator
(VCXO) devices are designed to meet today’s requirements for 2.5 V
and 3.3 V LVPECL clock generation applications. These devices use a
high Q fundamental mode crystal and Phase Locked Loop (PLL)
multiplier to provide a wide range of frequencies from 60 MHz to 700
MHz (factory configurable per user specifications) with a pullable
range of
±100
ppm and a frequency stability of
±50
ppm. The
silicon−based PureEdget products design provides users with
exceptional frequency stability and reliability. They produce an ultra
low jitter and phase noise LVPECL differential output.
The NBVSBAXXX series are members of ON Semiconductor’s
PureEdget clock family that provides accurate and precision clock
generation solutions.
Available in the industry standard 5.0 x 7.0 x 1.8 mm and in a new
3.2 x 5.0 x 1.2 mm SMD (CLCC) package on 16 mm tape and reel in
quantities of 1,000.
Features
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MARKING DIAGRAM
6 PIN CLCC
LN SUFFIX
CASE 848AB
NBVSBAXXX
XXX.XXXX
AWLYYWWG
6 PIN CLCC
LU SUFFIX
CASE 848AC
NBVSBAXXX
XXX.XXXX
A
WL
YY
WW
G
NBVSBAXXX
XXX.XXXX
AWLYYWWG
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LVPECL Differential Output
Operating Range: 2.5 V
±5%,
3.3 V
±10%
Ultra Low Jitter and Phase Noise
−
0.5 ps (12 kHz
−
20 MHz)
Factory Configurable Frequencies from 60 MHz to 700 MHz (see
Standard Frequencies in the Ordering Information Table in page 6)
Pullable Range Minimum of
±100
ppm
Frequency Stability of
±50
ppm
Control Voltage with Positive Slope
Voltage Control Linearity of
±10%
Uses High Q Fundamental Mode Crystal
Hermetically Sealed Ceramic SMD Package
These Devices are Pb−Free and RoHS Compliant
Networking
SONET
10 Gigabit Ethernet
Networking Base Stations
Broadcasting
= NBVSBAXXX (±50 ppm)
= Output Frequency (MHz)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Applications
©
Semiconductor Components Industries, LLC, 2011
April, 2011
−
Rev. 2
1
Publication Order Number:
NBVSBA011/D
NBVSBAXXX Series
V
DD
6
CLK CLK
5 4
PLL
Clock
Multiplier
1
V
C
2
OE
3
GND
Figure 1. Simplified Logic Diagram
V
C
OE
GND
1
2
3
6
5
4
V
DD
CLK
CLK
Figure 2. Pin Connections
(Top View)
Table 1. PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
Symbol
V
C
(Note 1)
OE
GND
CLK
CLK
V
DD
I/O
Analog Input
LVTTL/LVCMOS
Control Input
Power Supply
LVPECL Output
LVPECL Output
Power Supply
Description
Analog control voltage input pin that adjusts output oscillation frequency. f
0
=V
C
= 1.65 V
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
Ground at 0 V. Electrical and Case Ground.
Non−Inverted Clock Output. Typically loaded with 50
W
receiver termination resistor to
V
TT
= V
DD
−
2 V.
Inverted Clock Output. Typically loaded with 50
W
receiver termination resistor
to V
TT
= V
DD
−
2 V.
Positive Power Supply Voltage. Voltage should not exceed 2.5 V
±5%
and 3.3 V
±10%.
1. Control voltage has a positive slope with a linearity of
±10%;
V
C
= 1.65 V
±
1 V.
Table 2. OUTPUT ENABLE TRI−STATE FUNCTION
OE Pin
Open
HIGH Level
LOW Level
Output Pins
Active
Active
High Z
Table 3. ATTRIBUTES
Characteristic
Internal Default State Resistor
ESD Protection
Human Body Model
Machine Model
Value
170 kW
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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2
NBVSBAXXX Series
Table 4. MAXIMUM RATINGS
Symbol
V
DD
V
IN
I
out
T
A
T
stg
T
sol
Parameter
Positive Power Supply
Control Input (V
C
and OE)
LVPECL Output Current
Operating Temperature Range
Storage Temperature Range
Wave Solder
See Figure 4
Continuous
Surge
Condition 1
GND = 0 V
V
IN
≤
V
DD
+ 200 mV
V
IN
≥
GND
−
200 mV
25
50
−40
to +85
−55
to +120
260
Condition 2
Rating
4.6
Units
V
V
mA
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. DC CHARACTERISTICS
(V
DD
= 2.5 V
±
5%; 3.3 V
±
10%, GND = 0 V, T
A
=
−40°C
to +85°C) (Note 3)
Symbol
I
DD
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
V
OUTPP
Characteristic
Power Supply Current
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Output HIGH Voltage
Output LOW Voltage
Output Voltage Amplitude
OE
OE
OE
OE
2000
GND
−
200
−100
−100
V
DD
−1195
V
DD
−1945
700
Conditions
Min.
Typ.
90
Max.
110
V
DD
800
+100
+100
V
DD
−945
V
DD
−1600
Units
mA
mV
mV
mA
mA
mV
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measurement taken with outputs terminated with 50
W
to V
DD
−
2.0 V. See Figure 3.
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3
NBVSBAXXX Series
Table 6. AC CHARACTERISTICS
(V
DD
= 2.5
±5%,
V
DD
= 3.3
±10%,
GND = 0 V, T
A
= -40°C to +85°C)
Symbol
f
CLKOUT
Characteristic
Output Clock Frequency
Conditions
NBVSBA011
NBVSBA027
NBVSBA018
NBVSBA017
NBVSBA015
NBVSBA024
NBVSBA026
NBVSBA041
NBVSBA037
Df
t
jit
(f)
t
jitter
Frequency Stability
RMS Phase Jitter
Cycle to Cycle, RMS
Cycle to Cycle, Peak-to-Peak
Period, RMS
Period, Peak-to-Peak
t
OE/OD
F
P
V
C(bw)
t
DUTY_CYCLE
t
R
t
F
t
start
Output Enable/Disable Time
Crystal Pullability (Note 4)
Control Voltage Bandwidth
Output Clock Duty Cycle
(Measured at Cross Point)
Output Rise Time (20% and 80%)
Output Fall Time (80% and 20%)
Start-up Time
Aging
1
st
Year
Every Year After 1
st
0
≤
V
C
≤
3.3 V
- 3 dB
±100
20
45
50
245
245
1
55
400
400
5
3
1
(Note 5)
12 kHz to 20 MHz
1000 Cycles
1000 Cycles
10,000 Cycles
10,000 Cycles
0.5
2
10
1
6
Min.
Typ.
122.88
148.50
155.52
156.25
200.00
622.08
644.53
693.48
707.35
±50
0.9
8
30
4
20
200
ppm
ps
ps
ps
ps
ps
ns
ppm
KHz
%
ps
ps
ms
ppm
Max.
Units
MHz
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Gain transfer is positive with a rate of 130 ppm/V.
5. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration and first year aging.
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4
NBVSBAXXX Series
Table 7. PHASE NOISE PERFORMANCE
011
Parameter
f
NOISE
Characteristic
Output Phase−Noise Performance
Condition
100 Hz offset
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
122.88
MHZ
−90
−118
−127
−127
−134
−160
027
148.50
MHz
−90
−118
−127
−127
−134
−160
018
155.52
MHz
−90
−116
−126
−126
−134
−160
017
156.25
MHZ
−90
−116
−126
−126
−134
−160
015
200.00
MHz
−87
−114
−125
−125
−132
−158
Units
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Table 8. PHASE NOISE PERFORMANCE (continued)
024
Parameter
f
NOISE
Characteristic
Output Phase−Noise Performance
Condition
100 Hz offset
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
622.08
MHZ
−80
−106
−117
−117
−122
−150
026
644.53
MHZ
−86
−107
−116
−116
−125
−150
041
693.48
MHZ
−78
−105
−115
−115
−124
−149
037
707.35
MHZ
−78
−105
−115
−115
−124
−149
Units
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Table 9. RELIABILITY COMPLIANCE
Parameter
Shock
Solderability
Vibration
Solvent Resistance
Thermal Shock
Moisture Level Sensitivity
Mechanical
Mechanical
Mechanical
Mechanical
Environment
Environment
NBVSXXXXX
Q
Driver
Device
Q
Z
o
= 50
W
50
W
50
W
IN
Z
o
= 50
W
IN
Receiver
Device
Standard
Method
MIL−STD−833, Method 2002, Condition B
MIL−STD−833, Method 2003
MIL−STD−833, Method 2007, Condition A
MIL−STD−202, Method 215
MIL−STD−833, Method 1011, Condition A
MSL1 260°C per IPC/JEDEC J−STD−020D
V
TT
V
TT
= V
DD
−
2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D
−
Termination of ECL Logic Devices.)
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